Abstract: An embodiment of the present specification provides a method for preparing a catalyst for preparing a carbon nanotube, comprising: (a) dissolving a main catalyst precursor, a support precursor, a cocatalyst precursor and a precipitation inhibitor in a solvent to prepare a precursor solution; and (b) pyrolyzing the precursor solution by spraying the precursor solution into a reactor, wherein a mole fraction of the precipitation inhibitor to the cocatalyst precursor is 0.1 to 1.5.

Abstract: A wireless communication device support assembly is disclosed, including a support pole comprising a hollow interior, a first frame having a polygonal shape disposed on top of the support pole, a plurality of wireless communication devices disposed inside the first frame, at least one or more rotational advertising apparatuses controllably elevated in a direction parallel to a longitudinal direction of the support pole, a drive unit configured to elevate or lower the rotational advertising apparatus, and a plurality of lift ropes having first ends connected with tops of the rotational advertising apparatuses and second ends connected with the drive unit.

Abstract: The present invention relates to a support pole assembly for mounting an antenna and, particularly, to a support pole assembly for mounting an antenna, comprising: a support pole which is formed in a hollow structure and has an antenna device mounting hole formed at the circumferential surface thereof; an antenna device which is mounted to the support pole while passing through and covering the antenna device mounting hole and the rear portion of which is placed in the inner space of the support pole. Accordingly, the present invention provides an advantage in that the protrusion amount of the antenna device with respect to the support pole is reduced and thus the space required for mounting the antenna device can be reduced.

Abstract: The present invention relates to a clamping apparatus for an antenna device, and particularly, to a clamping apparatus including a rotation unit configured to rotate an antenna device in a horizontal direction, a tilting unit configured to rotate the antenna device in a vertical direction, and a connection arm configured to install at least one of the rotation unit and the tilting unit on a support pole so that the support pole is not positioned on a horizontal rotation path and a vertical rotation path of the antenna device, thereby reducing an installation space for an antenna device with respect to the support pole.

Abstract: The present disclosure relates to a polyimide-based resin film comprising a polyimide-based resin containing a polyimide repeating unit represented by Chemical Formula 1 and a polyimide repeating unit represented by Chemical Formula 2, a substrate for display device, and an optical device using the same.

Abstract: The gas sensor according to an exemplary embodiment of the present invention comprises: an FET device including one or more gate electrodes; a sensor array part including a plurality of sensors, in which a first electrode of each sensor is connected to at least one gate electrode of the plurality of gate electrodes in the FET device; and a controller detecting a gas using a current between a drain-source in response to voltage changes in the gate electrode of the FET device, wherein each sensor includes: a first electrode connected to a gate electrode of the FET device; a second electrode receiving an operating voltage through a switch controlled by the controller; and a detection film interposed between the first electrode and the second electrode.

Abstract: A method and apparatus for intra-prediction coding of video data are provided. The apparatus includes a decoder that is configured to decode, from a bitstream, a syntax element indicating an intra-prediction type of a current block of the video data, and an intra-predictor that is configured to generate a prediction block for the current block by selectively performing matrix based intra-prediction or regular intra-prediction based on the intra-prediction type of the current block indicated by the syntax element.

Abstract: A method and apparatus for intra-prediction coding of video data are provided. The apparatus includes a decoder that is configured to decode, from a bitstream, a syntax element indicating an intra-prediction type of a current block of the video data, and an intra-predictor that is configured to generate a prediction block for the current block by selectively performing matrix based intra-prediction or regular intra-prediction based on the intra-prediction type of the current block indicated by the syntax element.

Abstract: A phase correction circuit includes a plurality of signal paths configured to transmit multi-phase signals. The phase correction circuit further includes a loop circuit coupled to the plurality of signal paths, the loop circuit configured to correct phase skew among the multi-phase signals by averaging the phases of two signals which are obtained by synthesizing a signal of each of the signal paths with another signal of a signal path different from the corresponding signal path.

Abstract: An amplifier includes an amplification circuit, an equalization circuit, an output circuit, a first gain adjusting circuit, and a second gain adjusting circuit. The amplification circuit changes voltage levels of first and second amplification nodes based on first and second input signals. The equalization circuit changes the voltage levels of the first and second amplification nodes. The output circuit generates an output signal based on the voltage levels of the first and second amplification nodes. The first gain adjusting circuit changes voltage levels applied to the first and second amplification nodes based on the voltage levels of the first and second amplification nodes and a first gain control signal. The second gain adjusting circuit changes a voltage level of the output signal based on a second gain control signal.

Abstract: A power domain change circuit includes an input circuit and an output circuit. The input circuit is suitable for operating in a first power domain and generating first and second intermediate processing signals. The output circuit is suitable for operating in a second power domain and generating a final output signal by averaging and combining transition jitter components of the first and second intermediate processing signals.

Abstract: A phase correction circuit includes a plurality of signal paths configured to transmit multi-phase signals. The phase correction circuit further includes a loop circuit coupled to the plurality of signal paths, the loop circuit configured to correct phase skew among the multi-phase signals by averaging the phases of two signals which are obtained by synthesizing a signal of each of the signal paths with another signal of a signal path different from the corresponding signal path.

Abstract: A semiconductor apparatus includes a clock distribution network, a data output circuit, and a data input circuit. The clock distribution network receives a system clock signal and drives the system clock signal to a CMOS level and a CML level to signal in different manners. The data output circuit outputs data based on the clock signal driven to the CMOS level. The data input circuit receives data based on the clock signal driven to the CML level.

Abstract: A clock distribution circuit includes a global distribution circuit, a first local distribution circuit and a second local distribution circuit. The global distribution circuit receives external clock signals and generates internal clock signals and primary reference clock signal set according to the external clock signals. The first local distribution circuit receives the internal clock signals and the primary reference clock signal set and generates a secondary reference clock signal set according to the internal clock signals and the primary reference clock signal set. The second local distribution circuit receives the internal clock signals and the secondary reference clock signal set and generates a thirdly reference clock signal set according to the internal clock signals and the secondary reference clock signal set.

Abstract: A power domain change circuit includes an input circuit and an output circuit. The input circuit is suitable for operating in a first power domain and generating first and second intermediate processing signals. The output circuit is suitable for operating in a second power domain and generating a final output signal by averaging and combining transition jitter components of the first and second intermediate processing signals.

Abstract: Devices for reducing power consumption and skew for transmission of signals in a clock distribution circuit are described. A global distribution circuit is configured to divide external clock signals to generate first divided multiphase clock signals and divide one of the first divided multiphase clock signals to generate a reference clock signal. A local distribution circuit is configured to generate second divided multiphase clock signals according to a portion of the first divided multiphase clock signals and the reference clock signal.

Abstract: A phase correction circuit includes a plurality of signal paths configured to transmit multi-phase signals. The phase correction circuit further includes a loop circuit coupled to the plurality of signal paths, the loop circuit configured to correct phase skew among the multi-phase signals by averaging the phases of two signals which are obtained by synthesizing a signal of each of the signal paths with another signal of a signal path different from the corresponding signal path.

Abstract: A power domain change circuit includes an input circuit and an output circuit. The input circuit is suitable for operating in a first power domain and generating first and second intermediate processing signals. The output circuit is suitable for operating in a second power domain and generating a final output signal by averaging and combining transition jitter components of the first and second intermediate processing signals.

Abstract: A receiving circuit may include a first amplifying circuit, a second amplifying circuit, a third amplifying circuit, and a feedback circuit. The first amplifying circuit amplifies a first input signal and a second input signal to generate a first amplified signal and a second amplified signal, respectively. The second amplifying circuit amplifies the first amplified signal and the second amplified signal to generate a first preliminary output signal and a second preliminary output signal, respectively. The third amplifying circuit amplifies the first preliminary output signal and the second preliminary output signal to generate a first output signal and a second output signal, respectively. The feedback circuit changes voltage levels of the first amplified signal and the second amplified signal based on a current control signal, the first output signal, and the second output signal.

Abstract: A semiconductor system includes a semiconductor apparatus and an external apparatus. The semiconductor apparatus includes a calibration code generating circuit, a code shifting circuit, and a main driver. The calibration code generating circuit performs a calibration operation to generate a calibration code. The code shifting circuit changes, based on a shifting control signal, a value of the calibration code. A resistance value of the main driver may be set on the basis of the calibration code and a shifted calibration code. The external apparatus generates the shifting control signal based on the resistance value of the main driver.