Abstract: A receiving circuit may include a first amplifying circuit, a second amplifying circuit, a third amplifying circuit, and a feedback circuit. The first amplifying circuit amplifies a first input signal and a second input signal to generate a first amplified signal and a second amplified signal, respectively. The second amplifying circuit amplifies the first amplified signal and the second amplified signal to generate a first preliminary output signal and a second preliminary output signal, respectively. The third amplifying circuit amplifies the first preliminary output signal and the second preliminary output signal to generate a first output signal and a second output signal, respectively. The feedback circuit changes voltage levels of the first amplified signal and the second amplified signal based on a current control signal, the first output signal, and the second output signal.

Abstract: A semiconductor system includes a semiconductor apparatus and an external apparatus. The semiconductor apparatus includes a calibration code generating circuit, a code shifting circuit, and a main driver. The calibration code generating circuit performs a calibration operation to generate a calibration code. The code shifting circuit changes, based on a shifting control signal, a value of the calibration code. A resistance value of the main driver may be set on the basis of the calibration code and a shifted calibration code. The external apparatus generates the shifting control signal based on the resistance value of the main driver.

Abstract: A synchronization circuit includes a precharge circuit and a signal driving circuit. The precharge circuit precharges an output node to a first logic level. The signal driving circuit detects, in synchronization with a second dock signal having a phase leading a first clock signal, a logic level of an input signal and drives, in synchronization with the first clock signal, the output node to a second logic level according to the logic level of the input signal.

Abstract: A semiconductor system includes a semiconductor apparatus and an external apparatus. The semiconductor apparatus includes a calibration code generating circuit, a code shifting circuit, and a main driver. The calibration code generating circuit performs a calibration operation to generate a calibration code. The code shifting circuit changes, based on a shifting control signal, a value of the calibration code. A resistance value of the main driver may be set on the basis of the calibration code and a shifted calibration code. The external apparatus generates the shifting control signal based on the resistance value of the main driver.

Abstract: An amplifier includes a first input circuit, a second input circuit, a first compensation circuit, a second compensation circuit. The first input circuit changes a voltage level of the negative output node based on a first input signal. The second input circuit changes a voltage level of the positive output node based on a second input signal. The first compensation circuit changes the voltage level of the positive output node based on the first input signal. The second compensation circuit changes the voltage level of the negative output node based on the second output signal.

Abstract: A power domain change circuit includes an input circuit and an output circuit. The input circuit is suitable for operating in a first power domain and generating first and second intermediate processing signals. The output circuit is suitable for operating in a second power domain and generating a final output signal by averaging and combining transition jitter components of the first and second intermediate processing signals.

Abstract: Devices for reducing power consumption and skew for transmission of signals in a clock distribution circuit are described. A global distribution circuit is configured to divide external clock signals to generate first divided multiphase clock signals and divide one of the first divided multiphase clock signals to generate a reference clock signal. A local distribution circuit is configured to generate second divided multiphase clock signals according to a portion of the first divided multiphase clock signals and the reference clock signal.

Abstract: A synchronization circuit includes a precharge circuit and a signal driving circuit. The precharge circuit precharges an output node to a first logic level. The signal driving circuit detects, in synchronization with a second dock signal having a phase leading a first clock signal, a logic level of an input signal and drives, in synchronization with the first clock signal, the output node to a second logic level according to the logic level of the input signal.

Abstract: A signal transmission circuit of a semiconductor device includes a first emphasis circuit and a second emphasis circuit. The first emphasis circuit feeds a signal of an output node back to an input node. The first emphasis circuit may perform a first emphasis operation on a signal of the input node and the signal of the output node by adjusting a feedback time of the first emphasis circuit. The second emphasis circuit may be connected in parallel with the first emphasis circuit to perform a feedback of the signal of the output node to the input node. The second emphasis circuit may perform a second emphasis operation on the signal of the input node and the signal of the output node by adjusting a feedback time of the second emphasis circuit.

Abstract: An amplifier includes an amplification circuit, an equalization circuit, an output circuit, a first gain adjusting circuit, and a second gain adjusting circuit. The amplification circuit changes voltage levels of first and second amplification nodes based on first and second input signals. The equalization circuit changes the voltage levels of the first and second amplification nodes. The output circuit generates an output signal based on the voltage levels of the first and second amplification nodes. The first gain adjusting circuit changes voltage levels applied to the first and second amplification nodes based on the voltage levels of the first and second amplification nodes and a first gain control signal. The second gain adjusting circuit changes a voltage level of the output signal based on a second gain control signal.

Abstract: A signal transmission circuit of a semiconductor device includes a first emphasis circuit and a second emphasis circuit. The first emphasis circuit feeds a signal of an output node back to an input node. The first emphasis circuit may perform a first emphasis operation on a signal of the input node and the signal of the output node by adjusting a feedback time of the first emphasis circuit. The second emphasis circuit may be connected in parallel with the first emphasis circuit to perform a feedback of the signal of the output node to the input node. The second emphasis circuit may perform a second emphasis operation on the signal of the input node and the signal of the output node by adjusting a feedback time of the second emphasis circuit.

Abstract: A semiconductor device includes a circuit including an input coupled to a first node; and a first signal control circuit configured to determine a voltage of the first node in a low power mode, wherein the first signal control circuit sets a voltage of the first node to a first value in an n-th occurrence of the low power mode and a second value different from the first value in an m-th occurrence of the low power mode, and wherein n and m are two different natural numbers.

Abstract: A clock distribution network includes a global driver configured to receive a pair of clock signals to generate a pair of global clock signals, a clock transmission driver configured to amplify the pair of global clock signals to generate a pair of transmission clock signals, a first boosting circuit configured to boost voltage levels of the pair of transmission clock signals to generate a pair of first boosted clock signals, a first local driver configured to shift voltage levels of the pair of first boosted clock signals to generate a pair of first local clock signals, a second boosting circuit configured to boost voltage levels of the pair of first boosted clock signals to generate a pair of second boosted clock signals, and a second local driver configured to shift voltage levels of the pair of second boosted clock signals to generate a pair of second local clock signals.

Abstract: A clock distribution network includes a global driver configured to receive a pair of clock signals to generate a pair of global clock signals, a clock transmission driver configured to amplify the pair of global clock signals to generate a pair of transmission clock signals, a first boosting circuit configured to boost voltage levels of the pair of transmission clock signals to generate a pair of first boosted clock signals, a first local driver configured to shift voltage levels of the pair of first boosted clock signals to generate a pair of first local clock signals, a second boosting circuit configured to boost voltage levels of the pair of first boosted clock signals to generate a pair of second boosted clock signals, and a second local driver configured to shift voltage levels of the pair of second boosted clock signals to generate a pair of second local clock signals.

Abstract: An amplifier includes an amplification circuit, an equalization circuit, an output circuit, a first gain adjusting circuit, and a second gain adjusting circuit. The amplification circuit changes voltage levels of first and second amplification nodes based on first and second input signals. The equalization circuit changes the voltage levels of the first and second amplification nodes. The output circuit generates an output signal based on the voltage levels of the first and second amplification nodes. The first gain adjusting circuit changes voltage levels applied to the first and second amplification nodes based on the voltage levels of the first and second amplification nodes and a first gain control signal. The second gain adjusting circuit changes a voltage level of the output signal based on a second gain control signal.

Abstract: A signal receiver circuit includes a first amplification circuit and an offset compensation circuit. The first amplification circuit generates a first amplified signal and a second amplified signal by amplifying an input signal and a reference voltage. The offset compensation circuit adjusts voltage levels of the first and second amplified signals based on a DC level of the input signal and a voltage level of the reference voltage.

Abstract: A clocked latch circuit includes an amplification circuit, a latch circuit, a first current source, and a second current source. The amplification circuit changes voltage levels of first and second output signals based on a clock signal, a first input signal, and a second input signal. The latch circuit maintains the voltage levels of the first and second output signals based on a complementary signal of the clock signal. The first current source allows a first current to flow to activate the amplification circuit. The second current source allows a second current that is different from the first current to flow to activate the latch circuit.

Abstract: A semiconductor device includes a circuit including an input coupled to a first node; and a first signal control circuit configured to determine a voltage of the first node in a low power mode, wherein the first signal control circuit sets a voltage of the first node to a first value in an n-th occurrence of the low power mode and a second value different from the first value in an m-th occurrence of the low power mode, and wherein n and m are two different natural numbers.

Abstract: A semiconductor apparatus includes a calibration circuit and a main driver. The calibration circuit is configured to generate a first calibration code when set to have a positive offset and generate a second calibration code when set to have a negative offset complementary to the positive offset. The main driver is configured to set a resistance value of the main driver based on the first and second calibration codes.

Abstract: A transmitter may include an emphasis circuit suitable for generating a first pull-down driving signal in response to first data and delayed second data, and generating a first pull-up driving signal in response to second data and delayed first data, wherein the first and second data are a differential pair; a phase skew compensation circuit suitable for compensating for a phase skew between the first pull-up driving signal and the first pull-down driving signal to generate a second pull-up driving signal and a second pull-down driving signal; a pull-up driver suitable for pull-up driving an output node in response to the second pull-up driving signal; and a pull-down driver suitable for pull-down driving the output node in response to the second pull-down driving signal.