Patents by Inventor Hyo-Seok Choi
Hyo-Seok Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967847Abstract: A battery bank control device is provided for setting a power limit value of a battery bank in which a plurality of battery racks (BRs) are connected in parallel. The device includes: a voltage measurement unit measuring a voltage of each BR of the plurality of BRs; a first power limit calculation unit calculating a first power limit value according to a state of charge (SOC) calculated based on the voltage of each BR with respect to each BR; a capacity ratio calculation unit calculating a capacity ratio of each BR based on capacity information of the plurality of BRs; a second power limit calculation unit calculating a second power limit value using the capacity ratio and the first power limit value of each BR; and a battery bank power limit calculation unit calculating a battery bank power limit value using the second power limit value of each BR.Type: GrantFiled: March 16, 2020Date of Patent: April 23, 2024Assignee: LG ENERGY SOLUTION, LTD.Inventors: Sung Yul Yoon, Yoon Joon Choi, Hae In Choi, Jae Sung Im, Hyo Seok Lee
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Publication number: 20240120279Abstract: A semiconductor device may include a first film and a second film defining parts of a trench, a plug conductive film, a via, and a wiring in the trench. The trench may include a second sub-trench having a second width below a first sub-trench having a first width. The plug conductive film may extend from a first side of the first film to penetrate a bottom face of the trench. An uppermost face of the plug conducive film may be in the trench. The via may include an insulating liner between the plug conductive film and the first film. The uppermost face of the plug conductive film and at least a part of a side wall of the plug conductive film may be in contact with the wiring. An upper face of the insulating liner may be exposed by a bottom face of the second sub-trench.Type: ApplicationFiled: September 21, 2023Publication date: April 11, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Jeong Hyuk YIM, Wan Don KIM, Hyun Bae LEE, Hyo Seok CHOI, Geun Woo KIM
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Publication number: 20240063276Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.Type: ApplicationFiled: October 17, 2023Publication date: February 22, 2024Inventors: Heon Bok LEE, Dae Yong KIM, Wan Don KIM, Jeong Hyuk YIM, Won Keun CHUNG, Hyo Seok CHOI, Sang Jin HYUN
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Patent number: 11799004Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.Type: GrantFiled: March 15, 2022Date of Patent: October 24, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Heon Bok Lee, Dae Yong Kim, Wan Don Kim, Jeong Hyuk Yim, Won Keun Chung, Hyo Seok Choi, Sang Jin Hyun
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Publication number: 20220199790Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.Type: ApplicationFiled: March 15, 2022Publication date: June 23, 2022Inventors: Heon Bok LEE, Dae Yong KIM, Wan Don Kim, Jeong Hyuk YIM, Won Keun CHUNG, Hyo Seok CHOI, Sang Jin HYUN
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Patent number: 11296196Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.Type: GrantFiled: November 26, 2019Date of Patent: April 5, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Heon Bok Lee, Dae Yong Kim, Wan Don Kim, Jeong Hyuk Yim, Won Keun Chung, Hyo Seok Choi, Sang Jin Hyun
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Patent number: 11063036Abstract: A semiconductor device includes a substrate, a first recess formed in the substrate, a first source/drain filling the first recess, a vertical metal resistor on the first source/drain, and an insulating liner separating the metal resistor from the first source/drain, with the vertical metal resistor being between two gate electrodes.Type: GrantFiled: August 22, 2017Date of Patent: July 13, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyo Seok Choi, Chul Sung Kim, Jae Eun Lee
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Patent number: 10840374Abstract: A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.Type: GrantFiled: July 3, 2018Date of Patent: November 17, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chung-Hwan Shin, Sang-Bom Kang, Dae-Yong Kim, Jeong-Ik Kim, Chul-Sung Kim, Je-Hyung Ryu, Sang-Woo Lee, Hyo-Seok Choi
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Publication number: 20200176575Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.Type: ApplicationFiled: November 26, 2019Publication date: June 4, 2020Inventors: Heon Bok Lee, Dae Yong Kim, Wan Don Kim, Jeong Hyuk Yim, Won Keun Chung, Hyo Seok Choi, Sang Jin Hyun
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Patent number: 10403717Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes an isolation layer defining active portions of the substrate that are spaced apart from each other in a direction. The semiconductor device includes an epitaxial layer on the active portions. The semiconductor device includes a metal silicide layer on the epitaxial layer. Moreover, the semiconductor device includes a contact structure that only partially overlaps the metal silicide layer on the epitaxial layer. Related methods of forming semiconductor devices are also provided.Type: GrantFiled: August 25, 2017Date of Patent: September 3, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Do-Sun Lee, Chang-Woo Sohn, Chul-Sung Kim, Shigenobu Maeda, Young-Moon Choi, Hyo-Seok Choi, Sang-Jin Hyun
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Patent number: 10332984Abstract: A semiconductor device includes a substrate including an active region, a gate structure, source/drain regions, ones of the source/drain regions having an upper surface in which a recessed region is formed, a contact plug on the source/drain regions and extending in a direction substantially perpendicular to an upper surface of the substrate from an interior of the recessed region, a metal silicide film on an internal surface of the recessed region and including a first portion between a bottom surface of the recessed region and a lower surface of the contact plug and a second portion between a side wall of the recessed region and a side surface of the contact plug, and a metal layer connected to an upper portion of the metal silicide film and on a side surface of a region of the contact plug.Type: GrantFiled: March 29, 2017Date of Patent: June 25, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Hyo Seok Choi, Ryuji Tomita, Joon Gon Lee, Chul Sung Kim, Jae Eun Lee
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Publication number: 20180331218Abstract: A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.Type: ApplicationFiled: July 3, 2018Publication date: November 15, 2018Inventors: Chung-Hwan Shin, Sang-Bom Kang, Dae-Yong Kim, Jeong-lk Kim, Chul-Sung Kim, Je-Hyung Ryu, Sang-Woo Lee, Hyo-Seok Choi
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Patent number: 10043902Abstract: A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.Type: GrantFiled: December 9, 2015Date of Patent: August 7, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Chung-Hwan Shin, Sang-Bom Kang, Dae-Yong Kim, Jeong-Ik Kim, Chul-Sung Kim, Je-Hyung Ryu, Sang-Woo Lee, Hyo-Seok Choi
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Publication number: 20180151556Abstract: A semiconductor device includes a substrate, a first recess formed in the substrate, a first source/drain filling the first recess, a vertical metal resistor on the first source/drain, and an insulating liner separating the metal resistor from the first source/drain, with the vertical metal resistor being between two gate electrodes.Type: ApplicationFiled: August 22, 2017Publication date: May 31, 2018Inventors: Hyo Seok CHOI, Chul Sung KIM, Jae Eun LEE
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Publication number: 20180090583Abstract: A semiconductor device includes a substrate including an active region, a gate structure, source/drain regions, ones of the source/drain regions having an upper surface in which a recessed region is formed, a contact plug on the source/drain regions and extending in a direction substantially perpendicular to an upper surface of the substrate from an interior of the recessed region, a metal silicide film on an internal surface of the recessed region and including a first portion between a bottom surface of the recessed region and a lower surface of the contact plug and a second portion between a side wall of the recessed region and a side surface of the contact plug, and a metal layer connected to an upper portion of the metal silicide film and on a side surface of a region of the contact plug.Type: ApplicationFiled: March 29, 2017Publication date: March 29, 2018Inventors: Hyo Seok Choi, Ryuji Tomita, Joon Gon Lee, Chul Sung Kim, Jae Eun Lee
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Publication number: 20170352728Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes an isolation layer defining active portions of the substrate that are spaced apart from each other in a direction. The semiconductor device includes an epitaxial layer on the active portions. The semiconductor device includes a metal silicide layer on the epitaxial layer. Moreover, the semiconductor device includes a contact structure that only partially overlaps the metal silicide layer on the epitaxial layer. Related methods of forming semiconductor devices are also provided.Type: ApplicationFiled: August 25, 2017Publication date: December 7, 2017Inventors: Do-Sun Lee, Chang-Woo Sohn, Chul-Sung Kim, Shigenobu Maeda, Young-Moon Choi, Hyo-Seok Choi, Sang-Jin Hyun
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Patent number: 9768255Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes an isolation layer defining active portions of the substrate that are spaced apart from each other in a direction. The semiconductor device includes an epitaxial layer on the active portions. The semiconductor device includes a metal silicide layer on the epitaxial layer. Moreover, the semiconductor device includes a contact structure that only partially overlaps the metal silicide layer on the epitaxial layer. Related methods of forming semiconductor devices are also provided.Type: GrantFiled: January 26, 2016Date of Patent: September 19, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Do-Sun Lee, Chang-Woo Sohn, Chul-Sung Kim, Shigenobu Maeda, Young-Moon Choi, Hyo-Seok Choi, Sang-Jin Hyun
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Publication number: 20160308004Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes an isolation layer defining active portions of the substrate that are spaced apart from each other in a direction. The semiconductor device includes an epitaxial layer on the active portions. The semiconductor device includes a metal silicide layer on the epitaxial layer. Moreover, the semiconductor device includes a contact structure that only partially overlaps the metal silicide layer on the epitaxial layer. Related methods of forming semiconductor devices are also provided.Type: ApplicationFiled: January 26, 2016Publication date: October 20, 2016Inventors: Do-Sun LEE, Chang-Woo SOHN, Chul-Sung KIM, Shigenobu MAEDA, Young-Moon CHOI, Hyo-Seok CHOI, Sang-Jin HYUN
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Publication number: 20160233334Abstract: A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.Type: ApplicationFiled: December 9, 2015Publication date: August 11, 2016Inventors: Chung-Hwan Shin, Sang-Bom Kang, Dae-Yong Kim, Jeong-Ik Kim, Chul-Sung Kim, Je-Hyung Ryu, Sang-Woo Lee, Hyo-Seok Choi
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Patent number: 9240323Abstract: A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.Type: GrantFiled: March 7, 2013Date of Patent: January 19, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Chung-Hwan Shin, Sang-Bom Kang, Dae-Yong Kim, Jeong-Ik Kim, Chul-Sung Kim, Je-Hyung Ryu, Sang-Woo Lee, Hyo-Seok Choi