Patents by Inventor Hyo-Seung Nam

Hyo-Seung Nam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110241709
    Abstract: Disclosed herein are an apparatus and a method for measuring activity of a plating solution. The apparatus for measuring activity of a plating solution may include: a plating bath containing the plating solution for plating a plating object; a first electrode which is impregnated in the plating solution and has a plated body to measure current that flows in the plating solution and on the surface of the body in accordance with applied signal voltage; a second electrode which is impregnated in the plating solution to induce current from the first electrode or discharge current to the first electrode; a third electrode which controls the signal voltage applied to the first electrode to be constantly maintained; an impedance measurement unit which calculates an impedance value from the current measured in the first electrode; and a processing unit which displays a change of the calculated impedance value depending on a time.
    Type: Application
    Filed: July 19, 2010
    Publication date: October 6, 2011
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Young Ku Lyu, Tae Ho Kim, Jung Wook Seo, Hyo Seung Nam
  • Publication number: 20110135811
    Abstract: Disclosed is a solution for inhibiting palladium activity including an aqueous halogenic acid solution as a pre-treatment solution which may be used before an electroless plating of a printed circuit board to prevent bad plating and a method for preventing bad plating by using the same. More particularly, disclosed is a solution for inhibiting palladium activity including 0.1 to 10 mol of an aqueous halogenic acid solution as a pre-treatment solution which may be used before an ENIG plating or ENEPIG plating of a printed circuit board to prevent bad plating. Disclosed is also a method for preventing bad plating by minimizing defects of shorts between patterns which are caused by plating spreading during the surface treatment of a printed circuit board having fine patterns.
    Type: Application
    Filed: April 12, 2010
    Publication date: June 9, 2011
    Inventors: Hyuk-Jin Kwon, Hyo-Seung Nam, Tae-Ho Kim, Jong-Sik Kim, Jung-Wook Seo
  • Patent number: 7879153
    Abstract: It relates to a method for removing a surfactant, organic materials and chlorine ions remained on the surface of metal nanoparticles, prepared on an organic solvent phase including a surfactant. The method for cleaning metal nanoparticles herein is efficient to remove organic materials or chlorine ions remained on the surface of the nanoparticles. Not less than 90% of impurities may be removed by this method. As a result, the thickness of a multi layer ceramic capacitor (MLCC) can be reduced and a packing factor can be improved so that it allows thinner multi layer ceramic capacitors and improved utilities of metal nanoparticles as fuel cell catalysts, hydrogenation reaction catalysts, alternative catalysts of platinum (Pt) in chemical reactions and the like.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: February 1, 2011
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jung-Wook Seo, Hyo-Seung Nam, Young-Ku Lyu, Kyung-Mi Kim, Jong-Sik Kim, Tae-Ho Kim
  • Publication number: 20100031775
    Abstract: Provided is a method for preparing nickel nanoparticles capable of easily controlling particle sizes and shapes of the nickel nanoparticles and obtaining a high yield of the nickel nanoparticles using a process that is simpler than methods used to mass-produce the nickel nanoparticles. The method for preparing nickel nanoparticles may be useful to prepare nickel nanoparticles by mixing a nickel precursor and organic amine to prepare a mixture and heating the mixture.
    Type: Application
    Filed: December 23, 2008
    Publication date: February 11, 2010
    Inventors: Jung Wook Seo, Hyo Seung Nam, Ae Sul Im, Kyung Mi Kim, Jae Joon Lee
  • Publication number: 20100006446
    Abstract: A method for manufacturing a printed circuit board with an inner via hole, the method including applying a first current to both surfaces of a core layer having the inner via hole, so that a first plating layer grows centerwardly in an equal rate from all the directions of an inner wall of the inner via hole to close one entrance of the inner via hole, leaving a remaining space the inner via hole unfilled; and applying a second current to fill the remaining space of the inner via hole. Also, the manufacturing method does not require filling an inner via hole with an insulating ink, and forming a conductive layer on the insulating ink. Therefore, the method increases productive capacity and reduces manufacturing cost by simplifying the manufacturing process and reducing the lead time.
    Type: Application
    Filed: September 17, 2009
    Publication date: January 14, 2010
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Chi-Seong Kim, Hyo-Seung Nam, Seok-Hwan Ahn, Kwang-Ok Jeong, Kyung-Hwan Ko
  • Publication number: 20090029258
    Abstract: There is provided a method of preparing tin sulfide nanoparticles, in which tin sulfide particles are prepared selectively, easily controlled in size and morphology and can be massively produced more easily through a simpler process. The method includes: mixing a tin sulfide precursor with at least one surfactant into a mixture; and heating the mixture.
    Type: Application
    Filed: July 24, 2008
    Publication date: January 29, 2009
    Inventors: Jung Wook SEO, Hyo Seung NAM
  • Publication number: 20070199735
    Abstract: An aspect of the present invention features a printed circuit board. The board can comprise a core layer in which an inner via hole (IVH) is formed, a first plating layer that closes one entrance of the inner via hole, leaving a remaining space in the inner via hole unfilled; and a second plating layer that closes the other entrance of the inner via hole, filling the remaining space. Also, the present invention provides a printed circuit board and a manufacturing method thereof that do not require filling an inner via hole with an insulating ink, and forming a conductive layer on the insulating ink. Therefore, the present invention can increase productive capacity and reduce manufacturing cost by simplifying the manufacturing process and reducing the lead time.
    Type: Application
    Filed: February 23, 2007
    Publication date: August 30, 2007
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Chi-Seong Kim, Hyo-Seung Nam, Seok-Hwan Ahn, Kwang-Ok Jeong, Kyung-Hwan Ko