Abstract: The present disclosure relates to a polycarbonate resin composition, and more particularly, to a polycarbonate resin composition containing 90 wt % to 99 wt % of a polycarbonate resin, 0.3 wt % to 0.7 wt % of an anthraquinone-based black dye, and 0.2 wt % to 1.0 wt % of an acrylic polymeric chain extender, and a molded article containing the same.

Abstract: Embodiments described herein provide a semiconductor package comprising multiple dies encapsulated in multiple molding compounds. In one example, a semiconductor package comprises: a first die or die stack on a substrate; a first molding compound encapsulating the first die or die stack on the substrate; a second die or die stack on the first molding compound; and a second molding compound encapsulating the second die or die stack and at least one portion of the first molding compound. In this example, the first die or die stack is electrically coupled to the substrate using a first wire bond and the second die or die stack is electrically coupled to the substrate using a second wire bond. Additionally, the first molding compound encapsulates the first wire bond and the second molding compound encapsulates the second wire bond. Furthermore, a footprint of the second die overlaps a footprint of the first die.

Abstract: Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include an electronic component, a redistribution layer, and an interposer electrically coupling the redistribution layer and the electronic component. The interposer can have interconnect interfaces on a top side electrically coupled to the electronic component and interconnect interfaces on a bottom side electrically coupled to the redistribution layer. A density of the interconnect interfaces on the top side can be greater than a density of the interconnect interfaces on the bottom side. Associated systems and methods are also disclosed.

Abstract: Embodiments include systems in packages (SiPs) and a method of forming the SiPs. A SiP includes a package substrate and a first modularized sub-package over the package substrate, where the first modularized sub-package includes a plurality of electrical components, a first mold layer, and a redistribution layer. The SiP also includes a stack of dies over the package substrate, where the first modularized sub-package is disposed between the stack of dies. The SiP further includes a plurality of interconnects coupled to the stack of dies, the first modularized sub-package, and the package substrate, wherein the redistribution layer of the first modularized sub-package couples the stack of dies to the package substrate with the plurality of interconnects. The SiP may enable the redistribution layer of the first modularized sub-package to couple the electrical components to the stacked dies and the package substrate without a solder interconnect.

Abstract: A vertical-wire package-in-package includes at least two memory-die stacks that form respective memory modules that are stacked vertically on a bond-wire board. Each memory die in the memory-die stack includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the memory-die stack, the spacer, and a redistribution layer. At least two memory modules are assembled in a vertical-wire package-in-package.

Abstract: A paint composition suitable for hydraulic transfer painting of automotive parts is provided. The painting composition includes urethane beads, thereby imparting a good touch sensation to a painted surface and improving the durability of the painted automotive part. The paining composition includes a resin mixture containing an acrylic polyol resin and a polyester polyol resin, a solvent, an anti-sedimentation agent, a curing accelerator, a UV stabilizer, a polysiloxane-based surface conditioning agent, a wax, and a urethane bead.

Abstract: Semiconductor packages including active package substrates are described. In an example, the active package substrate includes an active die between a top substrate layer and a bottom substrate layer. The top substrate layer may include a via and the active die may include a die pad. An anisotropic conductive layer may be disposed between the via and the die pad to conduct electrical current unidirectionally between the via and the die pad. In an embodiment, the active die is a flash memory controller and a memory die is mounted on the top substrate layer and placed in electrical communication with the flash memory controller through the anisotropic conductive layer.

Abstract: Embodiments described herein are directed to a temporary interconnect for use in testing one or more devices (e.g., one or more dies, inductors, capacitors, etc.) formed in semiconductor package. In one scenario, a temporary interconnect acts an electrical bridge that electrically couples a contact pad on a surface of a substrate and the test pad. Coupling the contact pad and the test pad to each other enables the device(s) coupled the contact pad to be tested. Following testing, the temporary interconnect can be removed or severed so that an electrical break is formed in the conductive path between test pad and the contact pad.

Abstract: Embodiments described herein provide an anisotropic conductive film (ACF) positioned on a semiconductor package and techniques of using the ACF to test semiconductor devices positioned in or on the semiconductor package. In one example, a semiconductor package comprises: a die stack comprising one or more dies; a molding compound encapsulating the die stack; a substrate on the molding compound; a contact pad on a surface of the substrate and coupled to the die stack; a test pad on the surface of the substrate; a conductive path between the contact pad and the test pad, where an electrical break is positioned along the conductive path; and an ACF over the electrical break. Compressing the ACF by a test pin creates an electrical path that replaces the electrical break. Data can be acquired by test pin and provided to a test apparatus, which determines whether the dies in the die stack are operating properly.

Abstract: Embodiments described herein provide techniques for testing a semiconductor package by using a diode to couple a test pad to a contact pad. In one scenario, a package comprises a die stack comprising one or more dies and a molding compound encapsulating the die stack. In this package, a substrate is over the molding compound. Also, a test pad and a contact pad are on a surface of the substrate. The contact pad is coupled to the die stack. A diode couples the test pad to the contact pad. In one example, the test pad is coupled to a P side of the diode's P-N junction and the contact pad is coupled to an N side of the diode's P-N junction. In operation, current can flow from the test pad through the contact pad (and the die stack), but current cannot flow from the contact pad through the test pad.

Abstract: Apparatuses, systems and methods associated with integrated circuit (IC) package design are disclosed herein. In embodiments, an IC package may include a first die and a second die. The IC package may include a spacer located between the first die and the second die, the spacer includes glass, and a molding compound that at least partially encompasses the first die, the second die, and the spacer. Other embodiments may be described and/or claimed.

Abstract: Apparatuses, systems and methods associated with integrated circuit (IC) package design are disclosed herein. In embodiments, an IC package may include a first die and a second die. The IC package may include a spacer located between the first die and the second die, the spacer includes glass, and a molding compound that at least partially encompasses the first die, the second die, and the spacer. Other embodiments may be described and/or claimed.

Abstract: Embodiments include apparatuses, methods, and systems that may include a leadframe of a circuit package to conduct heat generated by an integrated circuit (IC) included in the circuit package, while being a part of an interconnect of the circuit package. In various embodiments, a circuit package may include a package substrate, and an IC attached to the package substrate. A leadframe may be disposed on the IC to conduct heat generated by the IC. In addition, the leadframe may be a part of an interconnect of the circuit package, and the leadframe may be electrically coupled to a component of the IC. Other embodiments may be described and/or claimed.

Abstract: An integrated circuit structure may be fabricated having a first integrated circuit package comprising a first integrated circuit device electrically attached to a first surface of a first substrate, a second integrated circuit package comprising a second integrated circuit device electrically attached to a first surface of a second substrate and an opening extending between a first surface of the second substrate and the second surface of the second substrate, and an interconnection structure electrically attached to the first surface of the first substrate, wherein a portion of the interconnection structure extends into the second substrate opening and wherein the interconnection structure is electrically attached to a first surface of the second substrate.

Abstract: A high density die package configuration is shown for use on system boards. In one example, an apparatus includes a system board, a first package mounted to the system board, a second package mounted to the system board, and an interface package mounted between the first and the second package and coupled directly to the first package and to the second package through the respective first and second packages.

Abstract: A vertical-wire package-in-package includes at least two memory-die stacks that form respective memory modules that are stacked vertically on a bond-wire board. Each memory die in the memory-die stack includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the memory-die stack, the spacer, and a redistribution layer. At least two memory modules are assembled in a vertical-wire package-in-package.

Abstract: Apparatuses, systems and methods associated with integrated circuit (IC) package design are disclosed herein. In embodiments, an IC package may include a first die and a second die. The IC package may include a spacer located between the first die and the second die, the spacer includes glass , and a molding compound that at least partially encompasses the first die, the second die, and the spacer. Other embodiments may be described and/or claimed.

Abstract: Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include an electronic component, a redistribution layer, and an interposer electrically coupling the redistribution layer and the electronic component. The interposer can have interconnect interfaces on a top side electrically coupled to the electronic component and interconnect interfaces on a bottom side electrically coupled to the redistribution layer. A density of the interconnect interfaces on the top side can be greater than a density of the interconnect interfaces on the bottom side. Associated systems and methods are also disclosed.

Abstract: An apparatus is provided which comprises: a first die having at least one bond pad; a first flexible layer comprising an anisotropic conductive material, wherein the first flexible layer is adjacent to the at least one bond pad such that it makes an electrical contact with the at least one bond pad; and a second flexible layer comprising a conductive metal, wherein the second flexible layer is adjacent to the first flexible layer.

Abstract: Semiconductor packages including active package substrates are described. In an example, the active package substrate includes an active die between a top substrate layer and a bottom substrate layer. The top substrate layer may include a via and the active die may include a die pad. An anisotropic conductive layer may be disposed between the via and the die pad to conduct electrical current unidirectionally between the via and the die pad. In an embodiment, the active die is a flash memory controller and a memory die is mounted on the top substrate layer and placed in electrical communication with the flash memory controller through the anisotropic conductive layer.