Patents by Inventor Hyoung-il Kim

Hyoung-il Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11145632
    Abstract: A high density die package configuration is shown for use on system boards. In one example, an apparatus includes a system board, a first package mounted to the system board, a second package mounted to the system board, and an interface package mounted between the first and the second package and coupled directly to the first package and to the second package through the respective first and second packages.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Juan E. Dominguez, Hyoung Il Kim, Bilal Khalaf, John Gary Meyers
  • Publication number: 20210288034
    Abstract: A vertical-wire package-in-package includes at least two memory-die stacks that form respective memory modules that are stacked vertically on a bond-wire board. Each memory die in the memory-die stack includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the memory-die stack, the spacer, and a redistribution layer. At least two memory modules are assembled in a vertical-wire package-in-package.
    Type: Application
    Filed: December 28, 2017
    Publication date: September 16, 2021
    Inventors: Hyoung IL Kim, Florence R. Pon, Yi Elyn Xu
  • Publication number: 20210280139
    Abstract: A pixel circuit includes a first pixel including a first switching element including a control electrode connected to a first node, an input electrode receiving a first power voltage and an output electrode connected to a second node, a second switching element including a control electrode receiving a first signal, an input electrode receiving a first data voltage and an output electrode connected to the first node, a first light emitting element including a first electrode connected to the second node and a second electrode receiving a second power voltage, a third switching element including a control electrode receiving a second signal, an input electrode connected to the second node and an output electrode connected to a third node and a fourth switching element including a control electrode receiving a third signal, an input electrode connected to the third node and an output electrode connected to a sensing line.
    Type: Application
    Filed: March 5, 2021
    Publication date: September 9, 2021
    Inventors: Hyoung-Wook KIM, Dong In KIM, Bong Im PARK, Woo Il PARK, Yong-Jin SHIN
  • Publication number: 20210280558
    Abstract: Apparatuses, systems and methods associated with integrated circuit (IC) package design are disclosed herein. In embodiments, an IC package may include a first die and a second die. The IC package may include a spacer located between the first die and the second die, the spacer includes glass , and a molding compound that at least partially encompasses the first die, the second die, and the spacer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 22, 2016
    Publication date: September 9, 2021
    Inventors: Mao Guo, Hyoung Il Kim, Yong She, Sireesha Gogineni
  • Publication number: 20210265305
    Abstract: Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include an electronic component, a redistribution layer, and an interposer electrically coupling the redistribution layer and the electronic component. The interposer can have interconnect interfaces on a top side electrically coupled to the electronic component and interconnect interfaces on a bottom side electrically coupled to the redistribution layer. A density of the interconnect interfaces on the top side can be greater than a density of the interconnect interfaces on the bottom side. Associated systems and methods are also disclosed.
    Type: Application
    Filed: December 31, 2016
    Publication date: August 26, 2021
    Applicant: Intel Corporation
    Inventors: Zhicheng Ding, Bin Liu, Yong She, Hyoung Il Kim
  • Patent number: 10892248
    Abstract: An apparatus is provided which comprises: a first die having at least one bond pad; a first flexible layer comprising an anisotropic conductive material, wherein the first flexible layer is adjacent to the at least one bond pad such that it makes an electrical contact with the at least one bond pad; and a second flexible layer comprising a conductive metal, wherein the second flexible layer is adjacent to the first flexible layer.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: January 12, 2021
    Assignee: Intel Corporation
    Inventor: Hyoung Il Kim
  • Publication number: 20200388587
    Abstract: Semiconductor packages including active package substrates are described. In an example, the active package substrate includes an active die between a top substrate layer and a bottom substrate layer. The top substrate layer may include a via and the active die may include a die pad. An anisotropic conductive layer may be disposed between the via and the die pad to conduct electrical current unidirectionally between the via and the die pad. In an embodiment, the active die is a flash memory controller and a memory die is mounted on the top substrate layer and placed in electrical communication with the flash memory controller through the anisotropic conductive layer.
    Type: Application
    Filed: August 21, 2020
    Publication date: December 10, 2020
    Inventors: Juan Eduardo DOMINGUEZ, Hyoung Il KIM
  • Patent number: 10863017
    Abstract: A method of receiving a call by recognizing a posture of a user in a portable terminal is provided. The method includes identifying whether a call reception event occurs, detecting a motion in which the user brings the portable terminal to an ear by using a posture detecting sensor, when the call reception event occurs, and connecting the call upon detecting the motion.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: December 8, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyoung-Il Kim, Tae-Jun Park
  • Publication number: 20200381406
    Abstract: A high density die package configuration is shown for use on system boards. In one example, an apparatus includes a system board, a first package mounted to the system board, a second package mounted to the system board, and an interface package mounted between the first and the second package and coupled directly to the first package and to the second package through the respective first and second packages.
    Type: Application
    Filed: September 29, 2017
    Publication date: December 3, 2020
    Inventors: Juan E. DOMINGUEZ, Hyoung Il KIM, Bilal KHALAF, John Gary MEYERS
  • Patent number: 10847450
    Abstract: A bond-wire system including a wire bond that is deflected above a dielectric ridge at a die edge. The deflected wire bond allows for both a lowered Z-profile and a reduced X-Y footprint. The bond-wire system may include a stacked-die configuration where a stacked die is wire bonded and the stacked-die bond wire is deflected above a dielectric ridge at the stacked die edge.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Saeed Shojaie, Hyoung Il Kim, Bilal Khalaf, Min-Tih Ted Lai
  • Publication number: 20200343221
    Abstract: Embodiments described herein provide a semiconductor package comprising multiple dies encapsulated in multiple molding compounds. In one example, a semiconductor package comprises: a first die or die stack on a substrate; a first molding compound encapsulating the first die or die stack on the substrate; a second die or die stack on the first molding compound; and a second molding compound encapsulating the second die or die stack and at least one portion of the first molding compound. In this example, the first die or die stack is electrically coupled to the substrate using a first wire bond and the second die or die stack is electrically coupled to the substrate using a second wire bond. Additionally, the first molding compound encapsulates the first wire bond and the second molding compound encapsulates the second wire bond. Furthermore, a footprint of the second die overlaps a footprint of the first die.
    Type: Application
    Filed: April 23, 2019
    Publication date: October 29, 2020
    Inventors: Florence PON, Yi XU, James ZHANG, Yuhong CAI, Tyler LEUTEN, William GLENNAN, Hyoung Il KIM
  • Patent number: 10790257
    Abstract: Semiconductor packages including active package substrates are described. In an example, the active package substrate includes an active die between a top substrate layer and a bottom substrate layer. The top substrate layer may include a via and the active die may include a die pad. An anisotropic conductive layer may be disposed between the via and the die pad to conduct electrical current unidirectionally between the via and the die pad. In an embodiment, the active die is a flash memory controller and a memory die is mounted on the top substrate layer and placed in electrical communication with the flash memory controller through the anisotropic conductive layer.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Juan Eduardo Dominguez, Hyoung Il Kim
  • Patent number: 10777486
    Abstract: Apparatuses and processes are disclosed for a substrate-free system in package that includes a through mold via Embodiments may include providing a circuit trace layer on top of a first side of a carrier, coupling a first set of one or more surface mount components to a first side of the circuit trace layer opposite the carrier, embedding the first set of the one or more surface mount components in a molding compound, exposing a second side of the circuit trace layer opposite the first side of the circuit trace layer, and coupling one or more electrical interconnects to serve as TMVs to the second side of the circuit trace layer. Embodiments may also include exposing the second side of the circuit trace layer by grinding the carrier. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventor: Hyoung Il Kim
  • Publication number: 20200243405
    Abstract: Embodiments described herein provide an anisotropic conductive film (ACF) positioned on a semiconductor package and techniques of using the ACF to test semiconductor devices positioned in or on the semiconductor package. In one example, a semiconductor package comprises: a die stack comprising one or more dies; a molding compound encapsulating the die stack; a substrate on the molding compound; a contact pad on a surface of the substrate and coupled to the die stack; a test pad on the surface of the substrate; a conductive path between the contact pad and the test pad, where an electrical break is positioned along the conductive path; and an ACF over the electrical break. Compressing the ACF by a test pin creates an electrical path that replaces the electrical break. Data can be acquired by test pin and provided to a test apparatus, which determines whether the dies in the die stack are operating properly.
    Type: Application
    Filed: January 29, 2019
    Publication date: July 30, 2020
    Inventor: Hyoung Il KIM
  • Patent number: 10727220
    Abstract: The present application relates to devices and techniques for a package on package multi-package integrated circuit. A component of the integrated circuit maybe located in a void formed in a circuit package of the multi-package integrated circuit. The void may be formed by fabricating a void structure with an internal void corresponding to the component. The void structure may be bonded to a first substrate of a first package in the multi-package integrated circuit. The first substrate and void structure may be encased in a mold compound. A sacrificial layer may be removed, exposing the void in the void structure. The component may be, for example, a through mold via. The first package may be coupled to a second package. Multi-package integrated circuit assemblies fabricated pursuant to the disclosure herein may comprise a higher density of electronic components, including passive electronic components.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventor: Hyoung Il Kim
  • Publication number: 20200235044
    Abstract: Embodiments include apparatuses, methods, and systems that may include a leadframe of a circuit package to conduct heat generated by an integrated circuit (IC) included in the circuit package, while being a part of an interconnect of the circuit package. In various embodiments, a circuit package may include a package substrate, and an IC attached to the package substrate. A leadframe may be disposed on the IC to conduct heat generated by the IC. In addition, the leadframe may be a part of an interconnect of the circuit package, and the leadframe may be electrically coupled to a component of the IC. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 20, 2017
    Publication date: July 23, 2020
    Inventor: Hyoung Il KIM
  • Publication number: 20200235018
    Abstract: Embodiments described herein are directed to a temporary interconnect for use in testing one or more devices (e.g., one or more dies, inductors, capacitors, etc.) formed in semiconductor package. In one scenario, a temporary interconnect acts an electrical bridge that electrically couples a contact pad on a surface of a substrate and the test pad. Coupling the contact pad and the test pad to each other enables the device(s) coupled the contact pad to be tested. Following testing, the temporary interconnect can be removed or severed so that an electrical break is formed in the conductive path between test pad and the contact pad.
    Type: Application
    Filed: January 17, 2019
    Publication date: July 23, 2020
    Inventors: Hyoung Il KIM, Yi XU, Florence PON
  • Publication number: 20200233033
    Abstract: Embodiments described herein provide techniques for wafer-level and panel-level testing of semiconductor devices. In one embodiment, a probe card comprises a probe card substrate and an array of test probes that extend outward from the probe card substrate. Each test probe has a blunt tip (i.e., a tip that is not sharp or pointed). An anisotropic conductive adhesive (ACA) may be formed on the test probes' blunt tips or disposed on a wafer or panel comprising contact pads formed therein or thereon. In one scenario, the test probes are brought in contact with the ACA, which is in contact with contact pads on or in a wafer or panel. The contacting of the ACA on the contact pads with the test probes forms electrical connections between test probes and the contact pads. In this way, the contact pads can be tested.
    Type: Application
    Filed: January 17, 2019
    Publication date: July 23, 2020
    Inventor: Hyoung Il KIM
  • Publication number: 20200227393
    Abstract: Embodiments include systems in packages (SiPs) and a method of forming the SiPs. A SiP includes a package substrate and a first modularized sub-package over the package substrate, where the first modularized sub-package includes a plurality of electrical components, a first mold layer, and a redistribution layer. The SiP also includes a stack of dies over the package substrate, where the first modularized sub-package is disposed between the stack of dies. The SiP further includes a plurality of interconnects coupled to the stack of dies, the first modularized sub-package, and the package substrate, wherein the redistribution layer of the first modularized sub-package couples the stack of dies to the package substrate with the plurality of interconnects. The SiP may enable the redistribution layer of the first modularized sub-package to couple the electrical components to the stacked dies and the package substrate without a solder interconnect.
    Type: Application
    Filed: January 14, 2019
    Publication date: July 16, 2020
    Inventors: Hyoung Il KIM, Bilal KHALAF, Juan E. DOMINGUEZ, John G. MEYERS
  • Publication number: 20200227386
    Abstract: Embodiments include a semiconductor package, a package on package system, and a method of forming the semiconductor package. The semiconductor package includes a first redistribution layer, a stack of dies on the first redistribution layer, a second redistribution layer over the stack of dies and the first redistribution layer, and a plurality of interconnects coupled to the stack of dies and the first and second redistribution layers. The interconnects may extend substantially vertical from a top surface of the first redistribution layer to a bottom surface of the second redistribution layer. The semiconductor package may also include a mold layer between the first redistribution layer and the second redistribution layer. The plurality of interconnects may be through mold vertical wire interconnects. The first and second redistribution layers may be dual-sided redistribution layers. The semiconductor package may further include adhesive layers coupled to the stack of dies.
    Type: Application
    Filed: January 14, 2019
    Publication date: July 16, 2020
    Inventor: Hyoung Il KIM