Patents by Inventor Hyoung-il Kim

Hyoung-il Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10497669
    Abstract: Disclosed is a die stack. The die stack may include a first plurality of dies and a second plurality of dies. Each of the plurality of dies may define a plurality of vias passing from a first side to a second side of the die. The plurality of dies may be stacked such that each of the plurality of vias in a first die are collinear with a respective via in a second die. At least one of the second plurality of dies may be wire bonded to at least one of the first plurality of dies.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: December 3, 2019
    Assignee: Intel Corporation
    Inventors: Juan Eduardo Dominguez, Hyoung Il Kim
  • Publication number: 20190355709
    Abstract: The present application relates to devices and techniques for a package on package multi-package integrated circuit. A component of the integrated circuit maybe located in a void formed in a circuit package of the multi-package integrated circuit. The void may be formed by fabricating a void structure with an internal void corresponding to the component. The void structure may be bonded to a first substrate of a first package in the multi-package integrated circuit. The first substrate and void structure may be encased in a mold compound. A sacrificial layer may be removed, exposing the void in the void structure. The component may be, for example, a through mold via. The first package may be coupled to a second package. Multi-package integrated circuit assemblies fabricated pursuant to the disclosure herein may comprise a higher density of electronic components, including passive electronic components.
    Type: Application
    Filed: August 1, 2019
    Publication date: November 21, 2019
    Inventor: Hyoung Il Kim
  • Publication number: 20190333895
    Abstract: An apparatus is provided which comprises: a first die having at least one bond pad; a first flexible layer comprising an anisotropic conductive material, wherein the first flexible layer is adjacent to the at least one bond pad such that it makes an electrical contact with the at least one bond pad; and a second flexible layer comprising a conductive metal, wherein the second flexible layer is adjacent to the first flexible layer.
    Type: Application
    Filed: December 20, 2016
    Publication date: October 31, 2019
    Applicant: Intel Corporation
    Inventor: Hyoung Il Kim
  • Patent number: 10446533
    Abstract: The present application relates to devices and techniques for a package on package multi-package integrated circuit. A component of the integrated circuit maybe located in a void formed in a circuit package of the multi-package integrated circuit. The void may be formed by fabricating a void structure with an internal void corresponding to the component. The void structure may be bonded to a first substrate of a first package in the multi-package integrated circuit. The first substrate and void structure may be encased in a mold compound. A sacrificial layer may be removed, exposing the void in the void structure. The component may be, for example, a through mold via. The first package may be coupled to a second package. Multi-package integrated circuit assemblies fabricated pursuant to the disclosure herein may comprise a higher density of electronic components, including passive electronic components.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventor: Hyoung Il Kim
  • Patent number: 10425524
    Abstract: A method of receiving a call by recognizing a posture of a user in a portable terminal is provided. The method includes identifying whether a call reception event occurs, detecting a motion in which the user brings the portable terminal to an ear by using a posture detecting sensor, when the call reception event occurs, and connecting the call upon detecting the motion.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: September 24, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyoung-Il Kim, Tae-Jun Park
  • Patent number: 10393799
    Abstract: Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include a substrate. The electronic device package can also include an electronic component disposed on the substrate and electrically coupled to the substrate. The electronic device package can further include a connector disposed on the substrate and electrically coupled to the substrate for communication with the electronic component. The connector can have a contact to interface with a mating connector and configured to provide a signal and/or power to the electronic component to facilitate testing the electronic component. Additionally, the electronic component can include an encapsulant material disposed on the substrate and at least partially encapsulating the electronic component and/or the connector. The contact can be accessible on a top side of the electronic device package to facilitate coupling the connector to a testing device.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventor: Hyoung Il Kim
  • Patent number: 10373545
    Abstract: Various embodiments relate to an apparatus and a method for determining a frame rate in an electronic device. The method for determining a frame rate in an electronic device, according to one embodiment, comprises the steps of: comparing 1st display data to be displayed at a reference time and 2nd display data to be displayed after the reference time; and determining a frame rate based on the comparison result. The method for determining a frame rate in an electronic device can be implemented through various embodiments.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: August 6, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyoung-Il Kim, Jung-Eun Lee
  • Publication number: 20190229093
    Abstract: Electronic device package technology is disclosed. An electronic device package can comprise a substrate. The electronic device package can also comprise first and second electronic components in a stacked configuration. Each of the first and second electronic components can include an electrical interconnect portion exposed toward the substrate. The electronic device package can further comprise a mold compound encapsulating the first and second electronic components. In addition, the electronic device package can comprise an electrically conductive post extending through the mold compound between the electrical interconnect portion of at least one of the first and second electronic components and the substrate. Associated systems and methods are also disclosed.
    Type: Application
    Filed: October 1, 2016
    Publication date: July 25, 2019
    Applicant: Intel Corporation
    Inventors: Juan E. Dominguez, Hyoung Il Kim, Mao Guo
  • Publication number: 20190181093
    Abstract: Semiconductor packages including active package substrates are described. In an example, the active package substrate includes an active die and an interposer embedded within a substrate laminate. The active die may be mounted on the interposer, and die pads of the active die may be electrically connected to a first contact array of the interposer. Accordingly, signal routing of the interposer may fan out an electrical signal from the embedded die pads to several vias in the substrate laminate. One or more memory dies of a memory stack may be mounted on substrate laminate and may be electrically connected to the vias. Accordingly, the embedded active die may control the memory stack.
    Type: Application
    Filed: September 30, 2016
    Publication date: June 13, 2019
    Inventors: Juan Eduardo DOMINGUEZ, Hyoung Il KIM
  • Publication number: 20190181072
    Abstract: A bond-wire system including a wire bond that is deflected above a dielectric ridge at a die edge. The deflected wire bond allows for both a lowered Z-profile and a reduced X-Y footprint. The bond-wire system may include a stacked-die configuration where a stacked die is wire bonded and the stacked-die bond wire is deflected above a dielectric ridge at the stacked die edge.
    Type: Application
    Filed: September 28, 2016
    Publication date: June 13, 2019
    Inventors: Saeed SHOJAIE, Hyoung IL KIM, Bilal KHALAF, Min-Tih TED LAI
  • Publication number: 20190101583
    Abstract: Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include a substrate. The electronic device package can also include an electronic component disposed on the substrate and electrically coupled to the substrate. The electronic device package can further include a connector disposed on the substrate and electrically coupled to the substrate for communication with the electronic component. The connector can have a contact to interface with a mating connector and configured to provide a signal and/or power to the electronic component to facilitate testing the electronic component. Additionally, the electronic component can include an encapsulant material disposed on the substrate and at least partially encapsulating the electronic component and/or the connector. The contact can be accessible on a top side of the electronic device package to facilitate coupling the connector to a testing device.
    Type: Application
    Filed: September 30, 2017
    Publication date: April 4, 2019
    Applicant: Intel Corporation
    Inventor: Hyoung Il Kim
  • Publication number: 20190103388
    Abstract: The present application relates to devices and techniques for a package on package multi-package integrated circuit. A component of the integrated circuit maybe located in a void formed in a circuit package of the multi-package integrated circuit. The void may be formed by fabricating a void structure with an internal void corresponding to the component. The void structure may be bonded to a first substrate of a first package in the multi-package integrated circuit. The first substrate and void structure may be encased in a mold compound. A sacrificial layer may be removed, exposing the void in the void structure. The component may be, for example, a through mold via. The first package may be coupled to a second package. Multi-package integrated circuit assemblies fabricated pursuant to the disclosure herein may comprise a higher density of electronic components, including passive electronic components.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventor: Hyoung Il Kim
  • Publication number: 20190067156
    Abstract: Embodiments of the present disclosure provide techniques and configurations for a semiconductor package with thermal fins, in accordance with some embodiments. In embodiments, a package assembly may comprise a die and a mold compound disposed on the die, to encapsulate the die. The package may further include a thermal solution comprising one or more thermal fins attached to the mold compound at their respective ends. The thermal fins may be disposed substantially flat on a top surface of the mold compound at a first temperature, and rise away from the top surface of the mold compound in response to a change of temperature to a second temperature, to reach an enclosure that surrounds the package assembly, to provide direct heat conductivity between the die and the enclosure. The second temperature may be greater than the first temperature. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: August 28, 2017
    Publication date: February 28, 2019
    Inventors: Hyoung Il Kim, Florence Pon, Yi Xu, Yuhong Cai, Min-Tih Lai, Leo Craft
  • Patent number: 10217435
    Abstract: Disclosed is a method of controlling an electronic device and an electronic device. The method may include: acquiring motion information of an electronic device; performing an inertial force correction for removing a part by an inertial force from the acquired motion information; and displaying a screen corresponding to the inertial force-corrected motion information.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: February 26, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Won Chae, Jung-Eun Lee, Hyoung-Il Kim
  • Publication number: 20190051582
    Abstract: Apparatuses and processes are disclosed for a substrate-free system in package that includes a through mold via Embodiments may include providing a circuit trace layer on top of a first side of a carrier, coupling a first set of one or more surface mount components to a first side of the circuit trace layer opposite the carrier, embedding the first set of the one or more surface mount components in a molding compound, exposing a second side of the circuit trace layer opposite the first side of the circuit trace layer, and coupling one or more electrical interconnects to serve as TMVs to the second side of the circuit trace layer. Embodiments may also include exposing the second side of the circuit trace layer by grinding the carrier. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 30, 2016
    Publication date: February 14, 2019
    Inventor: Hyoung Il KIM
  • Patent number: 10203739
    Abstract: An embodiment of the present invention relates to a device and a method for controlling power in an electronic device. The method for controlling power comprises an operation for determining a power consumption level necessary for the execution of a program in response to an execution input of the program, and an operation for executing the program on the basis of the power consumption level. Various other embodiments are also possible.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: February 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Won Chae, Hyoung-Il Kim, Jung-Eun Lee
  • Patent number: 10181456
    Abstract: A multi-package integrated circuit assembly can include a first electronic package having a first package substrate including a first die side and a first interface side. A first die can be electrically coupled to the first die side. A second electronic package can include a second package substrate having a second die side and a second interface side. A second die can be electrically coupled to the second die side. A conductive interconnect can be electrically coupled from the interface side of the first package substrate to the interface side of the second package substrate. A collective substrate can be attached to the first electronic package. For instance, the collective substrate can be located on a face of the first electronic package opposing the first package substrate. The collective substrate is electrically coupled to the first die and the second die through the first package substrate.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventor: Hyoung Il Kim
  • Publication number: 20180343337
    Abstract: A method of receiving a call by recognizing a posture of a user in a portable terminal is provided. The method includes identifying whether a call reception event occurs, detecting a motion in which the user brings the portable terminal to an ear by using a posture detecting sensor, when the call reception event occurs, and connecting the call upon detecting the motion.
    Type: Application
    Filed: July 17, 2018
    Publication date: November 29, 2018
    Inventors: Hyoung-IL Kim, Tae-Jun Park
  • Patent number: 10134716
    Abstract: A multi-package integrated circuit assembly can include a first electronic package having a first package substrate including a first die side and a first interface side. A first die can be electrically coupled to the first die side. A second electronic package can include a second package substrate having a second die side and a second interface side. A second die can be electrically coupled to the second die side. A metallic plated hole can be electrically coupled from the interface side of the first package substrate to the interface side of the second package substrate. A collective substrate can be attached to the first electronic package. For instance, the collective substrate can be located on a face of the first electronic package opposing the first package substrate. The collective substrate is electrically coupled to the first die and the second die through the first package substrate.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: November 20, 2018
    Assignee: Intel Corporatin
    Inventor: Hyoung Il Kim
  • Patent number: 10120424
    Abstract: Microelectronic device assembly including a component attached to substrate by at least a screw. The screw applies compressive force against a pad of a thermally and electrically conductive material having sufficiently low modulus to mitigate stress in addition to providing a thermal and electrical path between the component and the substrate. In some embodiments, the screw affixes a printed circuit board hosting one or more integrated circuit components to a motherboard, or passive heat sink. The pad may be deformed to assuage stress applied through the screw during assembly of the device and/or as the device experiences thermal cycling, for example associated with intermittent operation.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: November 6, 2018
    Assignee: Intel Corporation
    Inventor: Hyoung Il Kim