Patents by Inventor Hyoung-Sub Kim
Hyoung-Sub Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150132943Abstract: Provided is a method of manufacturing a semiconductor device. The method includes forming isolated contact filling portions and an etch control portion, the isolated contact filling portions filling contact holes defined in a support layer and are spaced apart from each other in a first direction and a second direction perpendicular to the first direction and the etch control layer surrounding the isolated contact filling portions, forming an interconnection layer on the isolated contact filling portions and the etch control portion, and forming interconnection patterns by photo-etching the interconnection layer, the isolated contact patterns, and the etch control portion, the interconnection patterns being relatively narrow in the first direction and relatively wide in the second direction.Type: ApplicationFiled: November 12, 2014Publication date: May 14, 2015Inventors: Dae-ik KIM, Hyoung-sub KIM, Yoo-sang HWANG
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Publication number: 20150132942Abstract: Provided is a method of manufacturing a semiconductor device. The method includes: forming bit line structures spaced apart from each other by first groove disposed in first direction, extending in first direction, and spaced apart from each other in second direction perpendicular to first direction, on substrate in which word line is buried; forming multilayer spacer on both sidewalls of bit line structure; forming sacrificial layer to fill first groove; forming second grooves spaced apart from each other in first direction and second direction, by patterning sacrificial layer; etching outermost spacer of multilayer spacer located in second groove; forming first supplementary spacer in second groove; forming insulating layer to fill second groove; and forming third grooves spaced apart from each other in first direction and second direction, on both sides of first supplementary spacer, by removing sacrificial layer and insulating layer.Type: ApplicationFiled: November 12, 2014Publication date: May 14, 2015Inventors: Dae-ik Kim, Hyoung-sub Kim, Yoo-sang Hwang, Ji-young Kim
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Patent number: 9012321Abstract: Provided is a method of manufacturing a semiconductor device. The method includes forming a sacrificial film as part of a process of forming a semiconductor device. The sacrificial film has a relatively high etch selectivity with respect to other materials of the semiconductor device so as to reduce loss of etching masks and improve the quality of a components (e.g., buried contacts) of the semiconductor device.Type: GrantFiled: May 21, 2014Date of Patent: April 21, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-ik Kim, Hyoung-sub Kim, Yoo-sang Hwang, Nak-jin Son, Ji-young Kim
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Publication number: 20150099344Abstract: Provided is a method of manufacturing a semiconductor device. The method includes forming a sacrificial film as part of a process of forming a semiconductor device. The sacrificial film has a relatively high etch selectivity with respect to other materials of the semiconductor device so as to reduce loss of etching masks and improve the quality of a components (e.g., buried contacts) of the semiconductor device.Type: ApplicationFiled: May 21, 2014Publication date: April 9, 2015Inventors: Dae-ik KIM, Hyoung-sub KIM, Yoo-sang HWANG, Nak-jin SON, Ji-young KIM
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Patent number: 8158976Abstract: Example embodiments relate to thin-film transistors (TFT) and methods for fabricating the same. A thin-film transistor according to example embodiments may include a gate, a gate insulation layer, a channel layer including a first oxide semiconductor layer and a second oxide semiconductor layer, and a source and drain on opposite sides of the channel layer. The first oxide semiconductor layer may have relatively large crystal grains compared to the second oxide semiconductor layer.Type: GrantFiled: February 26, 2010Date of Patent: April 17, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung-seok Son, Jang-yeon Kwon, Hyoung-sub Kim, Hoo-jeong Lee, Mi-ran Moon, Kyung Park
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Publication number: 20110017990Abstract: Example embodiments relate to thin-film transistors (TFT) and methods for fabricating the same. A thin-film transistor according to example embodiments may include a gate, a gate insulation layer, a channel layer including a first oxide semiconductor layer and a second oxide semiconductor layer, and a source and drain on opposite sides of the channel layer. The first oxide semiconductor layer may have relatively large crystal grains compared to the second oxide semiconductor layer.Type: ApplicationFiled: February 26, 2010Publication date: January 27, 2011Inventors: Kyoung-seok Son, Jang-yeon Kwon, Hyoung-sub Kim, Hoo-jeong Lee, Mi-ran Moon, Kyung Park
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Patent number: 7709346Abstract: A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner walls of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.Type: GrantFiled: January 19, 2007Date of Patent: May 4, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Jin Kim, Kyeong-Koo Chi, Chang-Jin Kang, Hyoung-Sub Kim, Mybong-Cheol Kim, Tae-Rin Chung, Sung-Hoon Chung, Ji-Young Kim
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Patent number: 7592215Abstract: According to embodiments of the invention, word line patterns are placed on a semiconductor substrate in a cell array region and at least one gate pattern is placed on the semiconductor substrate in a peripheral circuit region. Side walls of the word line patterns and the gate pattern are covered with word line spacers and gate spacers having the same width as that of the word line spacers, respectively. The semiconductor substrate having the word line spacers and the gate spacers is covered with an interlayer insulating layer. A self-aligned contact hole formed in the interlayer insulating layer penetrates a predetermined region between the word line patterns. The self-aligned contact hole is formed by etching the interlayer insulating layer and the word line spacers. The side walls of the self-aligned contact hole are covered with a self-aligned contact spacer having a width different from that of the gate spacers.Type: GrantFiled: August 10, 2006Date of Patent: September 22, 2009Assignee: Samsung Electronics Co., Ltd.Inventor: Hyoung-Sub Kim
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Publication number: 20080081432Abstract: A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner wails of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.Type: ApplicationFiled: January 19, 2007Publication date: April 3, 2008Inventors: Yong-Jin KIM, Kyeong-Koo Chi, Chang-Jin Kang, Hyoung-Sub Kim, Mybong-Cheol Kim, Tae-Rin Chung, Sung-Hoon Chung, Ji-Young Kim
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Publication number: 20070077709Abstract: According to embodiments of the invention, word line patterns are placed on a semiconductor substrate in a cell array region and at least one gate pattern is placed on the semiconductor substrate in a peripheral circuit region. Side walls of the word line patterns and the gate pattern are covered with word line spacers and gate spacers having the same width as that of the word line spacers, respectively. The semiconductor substrate having the word line spacers and the gate spacers is covered with an interlayer insulating layer. A self-aligned contact hole formed in the interlayer insulating layer penetrates a predetermined region between the word line patterns. The self-aligned contact hole is formed by etching the interlayer insulating layer and the word line spacers. The side walls of the self-aligned contact hole are covered with a self-aligned contact spacer having a width different from that of the gate spacers.Type: ApplicationFiled: August 10, 2006Publication date: April 5, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Hyoung-Sub KIM
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Patent number: 7183600Abstract: A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner walls of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.Type: GrantFiled: June 2, 2004Date of Patent: February 27, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Jin Kim, Kyeong-Koo Chi, Chang-Jin Kang, Hyoung-Sub Kim, Myeong-Cheol Kim, Tae-Rin Chung, Sung-Hoon Chung, Ji-Young Kim
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Patent number: 7135744Abstract: According to embodiments of the invention, word line patterns are placed on a semiconductor substrate in a cell array region and at least one gate pattern is placed on the semiconductor substrate in a peripheral circuit region. Side walls of the word line patterns and the gate pattern are covered with word line spacers and gate spacers having the same width as that of the word line spacers, respectively. The semiconductor substrate having the word line spacers and the gate spacers is covered with an interlayer insulating layer. A self-aligned contact hole formed in the interlayer insulating layer penetrates a predetermined region between the word line patterns. The self-aligned contact hole is formed by etching the interlayer insulating layer and the word line spacers. The side walls of the self-aligned contact hole are covered with a self-aligned contact spacer having a width different from that of the gate spacers.Type: GrantFiled: February 3, 2004Date of Patent: November 14, 2006Assignee: Samsung Electronics Co., Ltd.Inventor: Hyoung-Sub Kim
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Patent number: 7057242Abstract: An integrated circuit transistor includes an active region in a substrate, elongated along a first direction. A gate pattern is disposed on the substrate and crosses the active region along a second direction transverse to the first direction. The gate pattern includes an access gate portion disposed on the active region and narrowed at a central portion thereof. The gate pattern may further include a pass gate portion adjoining the access gate portion at the point beyond the edge of the active region, the pass gate portion having a lesser extent along the first direction than the access gate portion.Type: GrantFiled: October 3, 2002Date of Patent: June 6, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-young Kim, Hyoung-sub Kim
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Publication number: 20050275014Abstract: Embodiments of the invention are directed to an integrated circuit device and a method for forming the device. In some embodiments of the invention, two types of transistors are formed on a single substrate, transistors: transistors having a recessed gate, and transistors having a planer gate electrode. In other embodiments, transistors having a recessed gate are formed in multiple areas of the same substrate. Additionally, gates of the transistors in more than one region may be formed simultaneously.Type: ApplicationFiled: August 1, 2005Publication date: December 15, 2005Applicant: Samsung Electronics Co., Ltd.Inventors: Ji-Young Kim, Hyoung-Sub Kim
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Patent number: 6939765Abstract: Embodiments of the invention are directed to an integrated circuit device and a method for forming the device. In some embodiments of the invention, two types of transistors are formed on a single substrate, transistors: transistors having a recessed gate, and transistors having a planer gate electrode. In other embodiments, transistors having a recessed gate are formed in multiple areas of the same substrate. Additionally, gates of the transistors in more than one region may be formed simultaneously.Type: GrantFiled: August 26, 2003Date of Patent: September 6, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Young Kim, Hyoung-Sub Kim
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Publication number: 20050014338Abstract: Embodiments of the invention are directed to an integrated circuit device and a method for forming the device. In some embodiments of the invention, two types of transistors are formed on a single substrate, transistors: transistors having a recessed gate, and transistors having a planer gate electrode. In other embodiments, transistors having a recessed gate are formed in multiple areas of the same substrate. Additionally, gates of the transistors in more than one region may be formed simultaneously.Type: ApplicationFiled: August 26, 2003Publication date: January 20, 2005Applicant: Samsung Electronics Co., Ltd.Inventors: Ji-Young Kim, Hyoung-Sub Kim
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Publication number: 20050001252Abstract: A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner walls of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.Type: ApplicationFiled: June 2, 2004Publication date: January 6, 2005Inventors: Yong-Jin Kim, Kyeong-Koo Chi, Chang-Jin Kang, Hyoung-Sub Kim, Myeong-Cheol Kim, Tae-Rin Chung, Sung-Hoon Chung, Ji-Young Kim
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Publication number: 20040155282Abstract: According to embodiments of the invention, word line patterns are placed on a semiconductor substrate in a cell array region and at least one gate pattern is placed on the semiconductor substrate in a peripheral circuit region. Side walls of the word line patterns and the gate pattern are covered with word line spacers and gate spacers having the same width as that of the word line spacers, respectively. The semiconductor substrate having the word line spacers and the gate spacers is covered with an interlayer insulating layer. A self-aligned contact hole formed in the interlayer insulating layer penetrates a predetermined region between the word line patterns. The self-aligned contact hole is formed by etching the interlayer insulating layer and the word line spacers. The side walls of the self-aligned contact hole are covered with a self-aligned contact spacer having a width different from that of the gate spacers.Type: ApplicationFiled: February 3, 2004Publication date: August 12, 2004Inventor: Hyoung-Sub Kim
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Patent number: 6696722Abstract: A storage node of a DRAM cell capacitor includes a first insulating layer in which a bit line pattern is formed, a second insulating layer formed on the first insulating layer of which material is different from that of the second insulating layer, a first conductive layer formed on the second insulating layer that has an etching rate different from that of the first conductive layer, a material layer formed on the first conductive layer, which has a smaller width than the first conductive layer and is made of material with different etching characteristics from that of the first conductive layer, a second conductive layer that is formed on the material layer and has the same width as that of the material layer, and a sidewall conductive spacer that is an contact with the second conductive layer and the material layer and is formed on the top surface of the first conductive layer and on sides of the material layer and the second conductive layer.Type: GrantFiled: November 8, 2000Date of Patent: February 24, 2004Assignee: Samsung Electronics Co., Ltd.Inventor: Hyoung-Sub Kim
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Publication number: 20030107094Abstract: An integrated circuit transistor includes an active region in a substrate, elongated along a first direction. A gate pattern is disposed on the substrate and crosses the active region along a second direction transverse to the first direction. The gate pattern includes an access gate portion disposed on the active region and narrowed at a central portion thereof. The gate pattern may further include a pass gate portion adjoining the access gate portion at the point beyond the edge of the active region, the pass gate portion having a lesser extent along the first direction than the access gate portion.Type: ApplicationFiled: October 3, 2002Publication date: June 12, 2003Inventors: Ji-young Kim, Hyoung-sub Kim