Integration method of a semiconductor device having a recessed gate electrode
Embodiments of the invention are directed to an integrated circuit device and a method for forming the device. In some embodiments of the invention, two types of transistors are formed on a single substrate, transistors: transistors having a recessed gate, and transistors having a planer gate electrode. In other embodiments, transistors having a recessed gate are formed in multiple areas of the same substrate. Additionally, gates of the transistors in more than one region may be formed simultaneously.
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This is a Divisional of U.S. patent application Ser. No. 10/649,262, filed on Aug. 26, 2003, now pending, which claims priority from Korean Patent Application No. 2003-48079, filed on Jul. 13, 2003, which is incorporated by reference in is entirety.
TECHNICAL FIELDThis disclosure relates to an integration manufacturing method of a semiconductor memory device such as a Dynamic Random Access Memory (DRAM), and, more specifically, to a method to produce DRAM cells having a recessed gate and a planer gate electrode.
BACKGROUNDIntegrated circuits, such as ultra-large scale integrated (ULSI) circuits, can include as many as one billion transistors or more. Most typically, ULSI circuits are formed of Field Effect Transistors (FETs) formed in a Complementary Metal Oxide Semiconductor (CMOS) process. Each MOSFET includes a gate electrode formed over a channel region of the semiconductor substrate, which runs between a drain region and source region. To increase the device density and operation speed of the integrated circuits, the feature size of transistor within the circuits must be reduced. However, with the continued reduction in device size, sub-micron scale MOS transistors have to overcome many technical challenges. As the MOS transistors become narrower, that is, their channel length decreases, problems such as junction leakage, source/drain breakdown voltage, and data retention time become more pronounced.
One solution to decrease the physical dimension of ULSI circuits is to form recessed gate or “trench-type” transistors, which have a gate electrode buried in a groove formed in a semiconductor substrate. This type of transistor reduces short channel effects by effectively lengthening the effective channel length by having the gate extend into the semiconductor substrate. An example of a portion of a combined ULSI circuit including a standard transistor and a recessed gate transistor is illustrated in
Embodiments of the invention address these and other problems in the prior art.
BRIEF DESCRIPTION OF THE DRAWINGSThe invention will be understood more fully from the detailed description given below and from the accompanying drawings of embodiments of the invention, which, however, should not be taken to limit the invention to the specific embodiments, but are to facilitate explanation and understanding.
FIGS. 8 to 12 are cross-sectional diagrams illustrating a method of forming a MOSFET having a recessed gate and a planer gate electrode according to another embodiment of the present invention.
FIGS. 13 to 17 are cross-sectional diagrams illustrating a method of forming a MOSFET having a recessed gate and a planer gate electrode according to yet another embodiment of the present invention.
FIGS. 18 to 22 are cross-sectional diagrams illustrating of a method of forming a MOSFET having a recessed gate transistor in a cell region and a recessed gate in a peripheral region of a semiconductor substrate according to still a further embodiment of the present invention.
DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTIONIn the following detailed descriptions, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.
Embodiments of the invention can provide, compared to conventional memory circuits, an increase in effective channel length, a decrease in channel dosing, and improved qualities in junction leakage and data retention time in a memory circuit that includes at least two types of transistors on a single substrate: transistors having a recessed gate, and transistors having a planer gate electrode.
A manufacturing method of a semiconductor device of an embodiment of the present invention is described with reference to FIGS. 2 to 7. As shown in
An isolation region 15 is formed on a silicon substrate 10. A thin pad oxide film 18 is formed on the isolation 15 and over an active region in the memory cell array section. An etch stopper layer 20 is formed on the pad oxide film 18. The etch stopper layer 20 is preferably made of nitride, for example SiN, with a thickness of about 100 to 200 angstroms. A first oxide layer 25 is formed on the etch stopper layer 20. The first oxide layer 25 can be formed to a thickness of approximately 1000 angstroms in some embodiments.
A recess mask, for forming the recessed gates for the memory cells is formed in a photoresist layer 30 by conventional photolithography and etching processes. As shown in
As shown in
Next, as illustrated in
Some alternative methods for forming the memory circuit according to embodiments of the invention are illustrated in
Another embodiment of forming a semiconductor memory device is illustrated in
A recess mask for forming the recessed gates for the memory cells is formed in a photoresist layer 30 by conventional photolithography and etching processes. As shown in
As shown in
A further embodiment of forming a semiconductor memory device is illustrated in
A photoresist layer 30 is formed over the first oxide layer 25. Next, a recess mask for forming the recessed gates for the memory cells and for forming a planer gate hole 29 (
The first oxide layer 25 on the peripheral side of the substrate 10 is thicker than the first oxide layer 25 on the cell region portion of the substrate 10.
Next, as shown in
As illustrated in
Yet further methods to form a semiconductor memory device are illustrated in
A first oxide layer 25 is formed on the etch stopper layer 20. Next, a recess mask 30 is formed by conventional photolithography and etching processes. As shown in
As illustrated in
As shown in
As described above in detail, in embodiments of the present invention, a recessed gate cell and a planer gate electrode are simultaneously formed in the same photolithography step. This allows memory circuits to be developed so that the manufacturing processes will be reasonable without increasing the number of the photolithography steps.
Those skilled in the art recognize that the method of forming integrated circuits described herein can be implemented in many different variations. Therefore, although various embodiments are specifically illustrated and described herein, it will be appreciated that modifications and variations of the present invention are covered by the above teachings and within the purview of the appending claims without departing from the spirit and intended scope of the invention
Claims
1. A memory device, comprising:
- a substrate divided into a memory cell region and a peripheral circuit region;
- a plurality of memory cells having recessed gates formed in the memory cell region; and
- at least one transistor in the peripheral circuit region, the transistor including: a channel region formed between a source region and a drain region, a gate structure disposed over the channel region, and a resistance-reducing layer formed over the source and drain regions.
2. The memory device of claim 1 wherein the resistance-reducing layer comprises Cobalt.
3. The memory device of claim 2 wherein the resistance-reducing layer comprises a Cobalt-Silicon material.
4. The memory device of claim 1, further comprising an epitaxially grown silicon structure disposed between the source and drain regions and the resistance-reducing layer.
5. The memory device of claim 4 wherein the epitaxially grown silicon structure is formed by SEG (Selective Epitaxial Growing).
6. A memory device comprising:
- a substrate divided into a cell region and a peripheral region;
- a plurality of memory cells formed in the cell region, the plurality of memory cells each having a recessed gate structure; and
- a plurality of transistors in the peripheral region, the plurality of transistors each having a recessed gate structure.
7. The memory device of claim 6 wherein gates of the memory cells in the cell region and gates of the cells in the peripheral region are formed simultaneously.
Type: Application
Filed: Aug 1, 2005
Publication Date: Dec 15, 2005
Applicant: Samsung Electronics Co., Ltd. (Suwon-si)
Inventors: Ji-Young Kim (Gyeonggi-do), Hyoung-Sub Kim (Gyeonggi-do)
Application Number: 11/195,525