Patents by Inventor Hyoung-Sub Kim

Hyoung-Sub Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240263295
    Abstract: A deposition apparatus includes: a chamber; a deposition source disposed in the chamber; a rotating plate disposed in the chamber, where an inkjet head is fixed to the rotating plate to allow a nozzle plate of the inkjet head to be vertically aligned with the deposition source; and a first driving unit disposed in the chamber, where the first driving unit rotates the rotating plate about a vertical axis.
    Type: Application
    Filed: November 16, 2023
    Publication date: August 8, 2024
    Inventors: Jae Sik KIM, Woo Yong SUNG, Seung Ho YOON, Hyoung Sub LEE, Hye Min LEE
  • Patent number: 11705503
    Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: July 18, 2023
    Inventors: Jin Bum Kim, MunHyeon Kim, Hyoung Sub Kim, Tae Jin Park, Kwan Heum Lee, Chang Woo Noh, Maria Toledano Lu Que, Hong Bae Park, Si Hyung Lee, Sung Man Whang
  • Patent number: 11439222
    Abstract: The proposed is directed to a shampoo assisting device that is mounted on a wash basin, a bathtub, a sink, etc. with a simple configuration to allow the user to be shampooed while lying down. The shampoo assisting device includes a main body having a locking part provided on one side and a headrest part provided on the other side to support a user's head, and a first support protruding from a lower portion of the main body so as to be closely supported by a bottom surface of a wash basin.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: September 13, 2022
    Inventor: Hyoung-Sub Kim
  • Publication number: 20220015520
    Abstract: The proposed is directed to a shampoo assisting device that is mounted on a wash basin, a bathtub, a sink, etc. with a simple configuration to allow the user to be shampooed while lying down. The shampoo assisting device includes a main body having a locking part provided on one side and a headrest part provided on the other side to support a user's head, and a first support protruding from a lower portion of the main body so as to be closely supported by a bottom surface of a wash basin.
    Type: Application
    Filed: July 15, 2020
    Publication date: January 20, 2022
    Inventor: Hyoung-Sub KIM
  • Patent number: 11062818
    Abstract: Example embodiments relate to a stacking structure having a material layer formed on a graphene layer, and a method of forming the material layer on the graphene layer. In the stacking structure, when the material layer is formed on the graphene layer by using an ALD method, an intermediate layer as a seed layer may be formed on the graphene layer by using a linear type precursor.
    Type: Grant
    Filed: January 2, 2015
    Date of Patent: July 13, 2021
    Assignees: Samsung Electronics Co., Ltd., SUNGKYUNKWAN UNIVERSITY RESEARCH & BUSINESS FOUNDATION
    Inventors: Seong-jun Jeong, Seong-jun Park, Hyeon-jin Shin, Yea-hyun Gu, Hyoung-sub Kim, Jae-hyun Yang
  • Publication number: 20210013324
    Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction.
    Type: Application
    Filed: September 30, 2020
    Publication date: January 14, 2021
    Inventors: Jin Bum KIM, MunHyeon KIM, Hyoung Sub KIM, Tae Jin PARK, Kwan Heum LEE, Chang Woo NOH, Maria TOLEDANO LU QUE, Hong Bae PARK, Si Hyung LEE, Sung Man WHANG
  • Patent number: 10811541
    Abstract: A semiconductor device includes a gate electrode extending in a first direction on a substrate, a first active pattern extending in a second direction intersecting the first direction on the substrate to penetrate the gate electrode, the first active pattern including germanium, an epitaxial pattern on a side wall of the gate electrode, a first semiconductor oxide layer between the first active pattern and the gate electrode, and including a first semiconductor material, and a second semiconductor oxide layer between the gate electrode and the epitaxial pattern, and including a second semiconductor material. A concentration of germanium of the first semiconductor material may be less than a concentration of germanium of the first active pattern, and the concentration of germanium of the first semiconductor material may be different from a concentration of germanium of the second semiconductor material.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: October 20, 2020
    Assignees: Samsung Electronics Co., Ltd., Research & Business Foundation Sungkyunkwan University
    Inventors: Jin Bum Kim, Hyoung Sub Kim, Seong Heum Choi, Jin Yong Kim, Tae Jin Park, Seung Hun Lee
  • Publication number: 20190267494
    Abstract: A semiconductor device includes a gate electrode extending in a first direction on a substrate, a first active pattern extending in a second direction intersecting the first direction on the substrate to penetrate the gate electrode, the first active pattern including germanium, an epitaxial pattern on a side wall of the gate electrode, a first semiconductor oxide layer between the first active pattern and the gate electrode, and including a first semiconductor material, and a second semiconductor oxide layer between the gate electrode and the epitaxial pattern, and including a second semiconductor material. A concentration of germanium of the first semiconductor material may be less than a concentration of germanium of the first active pattern, and the concentration of germanium of the first semiconductor material may be different from a concentration of germanium of the second semiconductor material.
    Type: Application
    Filed: January 23, 2019
    Publication date: August 29, 2019
    Applicant: Research & Business Foundation Sungkyunkwan Univer sity
    Inventors: Jin Bum KIM, Hyoung Sub KIM, Seong Heum CHOI, Jin Yong KIM, Tae Jin PARK, Seung Hun LEE
  • Publication number: 20190198639
    Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction.
    Type: Application
    Filed: July 17, 2018
    Publication date: June 27, 2019
    Inventors: Jin Bum KIM, MunHyeon KIM, Hyoung Sub KIM, Tae Jin PARK, Kwan Heum LEE, Chang Woo NOH, Maria TOLEDANO LU QUE, Hong Bae PARK, Si Hyung LEE, Sung Man WHANG
  • Patent number: 10037999
    Abstract: A semiconductor device includes a substrate including an active region, a plurality of conductive line structures separate from the substrate, a plurality of contact plugs between the plurality of conductive line structures, a plurality of landing pads connected to a corresponding contact plug of the plurality of contact plugs, a landing pad insulation pattern between the plurality of landing pads, and a first insulation spacer between the landing pad insulation pattern and first conductive line structures from among the plurality of conductive line structures.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: July 31, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-ik Kim, Hyoung-sub Kim, Sung-eui Kim, Hoon Jeong
  • Patent number: 9953981
    Abstract: A method of manufacturing a semiconductor device includes: forming bit line structures spaced apart from each other by first groove disposed in first direction, extending in first direction, and spaced apart from each other in second direction perpendicular to first direction, on substrate in which word line is buried; forming multilayer spacer on both sidewalls of bit line structure; forming sacrificial layer to fill first groove; forming second grooves spaced apart from each other in first direction and second direction, by patterning sacrificial layer; etching outermost spacer of multilayer spacer located in second groove; forming first supplementary spacer in second groove; forming insulating layer to fill second groove; and forming third grooves spaced apart from each other in first direction and second direction, on both sides of first supplementary spacer, by removing sacrificial layer and insulating layer.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: April 24, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-ik Kim, Hyoung-sub Kim, Yoo-sang Hwang, Ji-young Kim
  • Patent number: 9754944
    Abstract: Provided is a method of manufacturing a semiconductor device. The method includes forming isolated contact filling portions and an etch control portion, the isolated contact filling portions filling contact holes defined in a support layer and are spaced apart from each other in a first direction and a second direction perpendicular to the first direction and the etch control layer surrounding the isolated contact filling portions, forming an interconnection layer on the isolated contact filling portions and the etch control portion, and forming interconnection patterns by photo-etching the interconnection layer, the isolated contact patterns, and the etch control portion, the interconnection patterns being relatively narrow in the first direction and relatively wide in the second direction.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: September 5, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-ik Kim, Hyoung-sub Kim, Yoo-sang Hwang
  • Patent number: 9613966
    Abstract: A semiconductor device includes a semiconductor substrate including a plurality of active areas, a bit line crossing the plurality of active areas, a direct contact connecting a first active area of the plurality of active areas with the bit line, an insulating spacer covering a side wall of the bit line and extending at a level lower than a level of an upper surface of the semiconductor substrate, a contact pad connected with a side wall of a second active area of the plurality of active areas, which neighbors the first active area, a first insulating pattern defining a contact hole exposing the insulating spacer and the contact pad, and a buried contact connected with the contact pad and filling the contact hole.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: April 4, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-ik Kim, Hyoung-sub Kim, Sung-eui Kim
  • Publication number: 20160322362
    Abstract: A method of manufacturing a semiconductor device includes: forming bit line structures spaced apart from each other by first groove disposed in first direction, extending in first direction, and spaced apart from each other in second direction perpendicular to first direction, on substrate in which word line is buried; forming multilayer spacer on both sidewalls of bit line structure; forming sacrificial layer to fill first groove; forming second grooves spaced apart from each other in first direction and second direction, by patterning sacrificial layer; etching outermost spacer of multilayer spacer located in second groove; forming first supplementary spacer in second groove; forming insulating layer to fill second groove; and forming third grooves spaced apart from each other in first direction and second direction, on both sides of first supplementary spacer, by removing sacrificial layer and insulating layer.
    Type: Application
    Filed: July 12, 2016
    Publication date: November 3, 2016
    Inventors: Dae-ik Kim, Hyoung-sub Kim, Yoo-sang Hwang, Ji-young Kim
  • Patent number: 9419000
    Abstract: Provided is a method of manufacturing a semiconductor device. The method includes: forming bit line structures spaced apart from each other by first groove disposed in first direction, extending in first direction, and spaced apart from each other in second direction perpendicular to first direction, on substrate in which word line is buried; forming multilayer spacer on both sidewalls of bit line structure; forming sacrificial layer to fill first groove; forming second grooves spaced apart from each other in first direction and second direction, by patterning sacrificial layer; etching outermost spacer of multilayer spacer located in second groove; forming first supplementary spacer in second groove; forming insulating layer to fill second groove; and forming third grooves spaced apart from each other in first direction and second direction, on both sides of first supplementary spacer, by removing sacrificial layer and insulating layer.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: August 16, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-ik Kim, Hyoung-sub Kim, Yoo-sang Hwang, Ji-young Kim
  • Patent number: 9349633
    Abstract: A method of manufacturing a semiconductor device includes forming an isolation layer on a substrate, where an active pattern is defined, forming an insulating interlayer on the active pattern of the substrate and the isolation layer, removing portions of the insulating interlayer, the active pattern and the isolation layer to form a first recess, forming a first contact in the first recess on a first region of the active pattern exposed by the first recess, removing portions of the active pattern and the isolation layer in the first recess by performing an isotropic etching process, to form an enlarged first recess, and filling the enlarged first recess to form a first spacer that surrounds a sidewall of the first contact.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: May 24, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-Ik Kim, Sung-Eui Kim, Hyoung-Sub Kim, Sung-Kwan Choi
  • Publication number: 20150380508
    Abstract: A semiconductor device includes a semiconductor substrate including a plurality of active areas, a bit line crossing the plurality of active areas, a direct contact connecting a first active area of the plurality of active areas with the bit line, an insulating spacer covering a side wall of the bit line and extending at a level lower than a level of an upper surface of the semiconductor substrate, a contact pad connected with a side wall of a second active area of the plurality of active areas, which neighbors the first active area, a first insulating pattern defining a contact hole exposing the insulating spacer and the contact pad, and a buried contact connected with the contact pad and filling the contact hole.
    Type: Application
    Filed: April 28, 2015
    Publication date: December 31, 2015
    Inventors: Dae-ik KIM, Hyoung-sub KIM, Sung-eui KIM
  • Publication number: 20150214146
    Abstract: A semiconductor device includes a substrate including an active region, a plurality of conductive line structures separate from the substrate, a plurality of contact plugs between the plurality of conductive line structures, a plurality of landing pads connected to a corresponding contact plug of the plurality of contact plugs, a landing pad insulation pattern between the plurality of landing pads, and a first insulation spacer between the landing pad insulation pattern and first conductive line structures from among the plurality of conductive line structures.
    Type: Application
    Filed: January 7, 2015
    Publication date: July 30, 2015
    Inventors: Dae-ik KIM, Hyoung-sub KIM, Sung-eui KIM, Hoon JEONG
  • Publication number: 20150194233
    Abstract: Example embodiments relate to a stacking structure having a material layer formed on a graphene layer, and a method of forming the material layer on the graphene layer. In the stacking structure, when the material layer is formed on the graphene layer by using an ALD method, an intermediate layer as a seed layer may be formed on the graphene layer by using a linear type precursor.
    Type: Application
    Filed: January 2, 2015
    Publication date: July 9, 2015
    Applicant: Sungkyunkwan University Research & Business Foundation
    Inventors: Seong-jun JEONG, Seong-jun PARK, Hyeon-jin SHIN, Yea-hyun GU, Hyoung-sub KIM, Jae-hyun YANG
  • Patent number: D986502
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: May 16, 2023
    Inventor: Hyoung-Sub Kim