Patents by Inventor Hyuek Jae Lee
Hyuek Jae Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240096728Abstract: A semiconductor package is provided. The semiconductor package comprises a first semiconductor die including a memory, a second semiconductor die including a memory and on the first semiconductor die, a dummy die on the semiconductor device and not including a memory, a heat sink on the dummy die and including a metal material and a mold film on side surfaces of each of the first semiconductor die, the second semiconductor die, the dummy die, and the heat sink. A width of the heat sink may decrease away from a top surface of the dummy die, and side surfaces of the heat sink may be curved.Type: ApplicationFiled: June 23, 2023Publication date: March 21, 2024Inventors: Jin Kyeong Seol, Hyuek Jae Lee
-
Patent number: 11887900Abstract: A semiconductor package includes a base including a first bonding structure; and a first semiconductor chip, including a second bonding structure, the second bonding structure being coupled to the first bonding structure of the base, wherein the first bonding structure includes: a test pad; a first pad being electrically connected to the test pad; and a first insulating layer, wherein the second bonding structure includes: a second pad being electrically connected to the first pad; and a second insulating layer being in contact with the first insulating layer, and wherein at least a portion of the test pad is in contact with the second insulating layer.Type: GrantFiled: July 6, 2021Date of Patent: January 30, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyuek Jae Lee, Tae Hun Kim, Ji Hwan Hwang, Ji Hoon Kim, Ji Seok Hong
-
Patent number: 11887968Abstract: A semiconductor package includes a base structure having a base pad, a first semiconductor chip on the base structure, and having a first connection pad bonded to the base pad, a first bonding structure including an base insulation layer of a base structure and a first lower insulation layer of the first semiconductor chip bonded to the base insulation layer, a second semiconductor chip on the first semiconductor chip, and having a second connection pad connected to the first through-electrode, and a second bonding structure including a first upper insulation layer of the first semiconductor chip, and a second lower insulation layer of the second semiconductor chip bonded to the first upper insulation layer, and the first upper insulation layer has a dummy insulation portion extending onto the base structure around the first semiconductor chip.Type: GrantFiled: October 5, 2021Date of Patent: January 30, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Hwan Hwang, Ji Hoon Kim, Ji Seok Hong, Tae Hun Kim, Hyuek Jae Lee
-
Publication number: 20230395523Abstract: A semiconductor package includes a substrate including a first semiconductor chip including a first wiring structure, a first bonding pad, and a first alignment key on the first wiring structure to be spaced apart in a first direction, a second semiconductor chip including a second wiring structure, a second bonding pad on the second wiring structure and connected to the first bonding pad, and a second alignment key on the second wiring structure to be spaced apart from the second bonding pad and not overlapping the first alignment key in the second direction, the first wiring structure including a first wiring pattern connected to the first bonding pad and not overlapping the first and second alignment keys in the second direction, and the second wiring structure including a second wiring pattern connected to the second bonding pad and not overlapping the first and second alignment keys in the second direction.Type: ApplicationFiled: August 17, 2023Publication date: December 7, 2023Inventors: Sang Cheon PARK, Young Min LEE, Dae-Woo KIM, Hyuek Jae LEE
-
Patent number: 11776916Abstract: A semiconductor package includes a substrate including a first semiconductor chip including a first wiring structure, a first bonding pad, and a first alignment key on the first wiring structure to be spaced apart in a first direction, a second semiconductor chip including a second wiring structure, a second bonding pad on the second wiring structure and connected to the first bonding pad, and a second alignment key on the second wiring structure to be spaced apart from the second bonding pad and not overlapping the first alignment key in the second direction, the first wiring structure including a first wiring pattern connected to the first bonding pad and not overlapping the first and second alignment keys in the second direction, and the second wiring structure including a second wiring pattern connected to the second bonding pad and not overlapping the first and second alignment keys in the second direction.Type: GrantFiled: March 12, 2021Date of Patent: October 3, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang Cheon Park, Young Min Lee, Dae-Woo Kim, Hyuek Jae Lee
-
Patent number: 11581257Abstract: A semiconductor package is provided. The semiconductor package includes a lower structure including an upper insulating layer and an upper pad; and a semiconductor chip provided on the lower structure and comprising a lower insulating layer and a lower pad. The lower insulating layer is in contact with and coupled to the upper insulating layer and the lower pad is in contact with and coupled to the upper pad, and a lateral side of the semiconductor chip extends between an upper side and a lower side of the semiconductor chip and comprises a recessed portion.Type: GrantFiled: June 4, 2021Date of Patent: February 14, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyuek Jae Lee, Ji Hoon Kim, Tae Hun Kim, Ji Seok Hong, Ji Hwan Hwang
-
Publication number: 20220068829Abstract: A semiconductor package includes a substrate including a first semiconductor chip including a first wiring structure, a first bonding pad, and a first alignment key on the first wiring structure to be spaced apart in a first direction, a second semiconductor chip including a second wiring structure, a second bonding pad on the second wiring structure and connected to the first bonding pad, and a second alignment key on the second wiring structure to be spaced apart from the second bonding pad and not overlapping the first alignment key in the second direction, the first wiring structure including a first wiring pattern connected to the first bonding pad and not overlapping the first and second alignment keys in the second direction, and the second wiring structure including a second wiring pattern connected to the second bonding pad and not overlapping the first and second alignment keys in the second direction.Type: ApplicationFiled: March 12, 2021Publication date: March 3, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Sang Cheon PARK, Young Min LEE, Dae-Woo KIM, Hyuek Jae LEE
-
Publication number: 20220028837Abstract: A semiconductor package includes a base structure having a base pad, a first semiconductor chip on the base structure, and having a first connection pad bonded to the base pad, a first bonding structure including an base insulation layer of a base structure and a first lower insulation layer of the first semiconductor chip bonded to the base insulation layer, a second semiconductor chip on the first semiconductor chip, and having a second connection pad connected to the first through-electrode, and a second bonding structure including a first upper insulation layer of the first semiconductor chip, and a second lower insulation layer of the second semiconductor chip bonded to the first upper insulation layer, and the first upper insulation layer has a dummy insulation portion extending onto the base structure around the first semiconductor chip.Type: ApplicationFiled: October 5, 2021Publication date: January 27, 2022Inventors: Ji Hwan HWANG, Ji Hoon KIM, Ji Seok HONG, Tae Hun KIM, Hyuek Jae LEE
-
Publication number: 20210335680Abstract: A semiconductor package includes a base including a first bonding structure; and a first semiconductor chip, including a second bonding structure, the second bonding structure being coupled to the first bonding structure of the base, wherein the first bonding structure includes: a test pad; a first pad being electrically connected to the test pad; and a first insulating layer, wherein the second bonding structure includes: a second pad being electrically connected to the first pad; and a second insulating layer being in contact with the first insulating layer, and wherein at least a portion of the test pad is in contact with the second insulating layer.Type: ApplicationFiled: July 6, 2021Publication date: October 28, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyuek Jae LEE, Tae Hun Kim, Ji Hwan Hwang, Ji Hoon Kim, Ji Seok Hong
-
Patent number: 11145626Abstract: A semiconductor package includes a base structure having a base pad, a first semiconductor chip on the base structure, and having a first connection pad bonded to the base pad, a first bonding structure including an base insulation layer of a base structure and a first lower insulation layer of the first semiconductor chip bonded to the base insulation layer, a second semiconductor chip on the first semiconductor chip, and having a second connection pad connected to the first through-electrode, and a second bonding structure including a first upper insulation layer of the first semiconductor chip, and a second lower insulation layer of the second semiconductor chip bonded to the first upper insulation layer, and the first upper insulation layer has a dummy insulation portion extending onto the base structure around the first semiconductor chip.Type: GrantFiled: October 1, 2019Date of Patent: October 12, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Ji Hwan Hwang, Ji Hoon Kim, Ji Seok Hong, Tae Hun Kim, Hyuek Jae Lee
-
Publication number: 20210296228Abstract: A semiconductor package is provided. The semiconductor package includes a lower structure including an upper insulating layer and an upper pad; and a semiconductor chip provided on the lower structure and comprising a lower insulating layer and a lower pad. The lower insulating layer is in contact with and coupled to the upper insulating layer and the lower pad is in contact with and coupled to the upper pad, and a lateral side of the semiconductor chip extends between an upper side and a lower side of the semiconductor chip and comprises a recessed portion.Type: ApplicationFiled: June 4, 2021Publication date: September 23, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyuek Jae Lee, Ji Hoon Kim, Tae Hun Kim, Ji Seok Hong, Ji Hwan Hwang
-
Patent number: 11088038Abstract: A semiconductor package includes a base including a first bonding structure; and a first semiconductor chip, including a second bonding structure, the second bonding structure being coupled to the first bonding structure of the base, wherein the first bonding structure includes: a test pad; a first pad being electrically connected to the test pad; and a first insulating layer, wherein the second bonding structure includes: a second pad being electrically connected to the first pad; and a second insulating layer being in contact with the first insulating layer, and wherein at least a portion of the test pad is in contact with the second insulating layer.Type: GrantFiled: July 11, 2019Date of Patent: August 10, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyuek Jae Lee, Tae Hun Kim, Ji Hwan Hwang, Ji Hoon Kim, Ji Seok Hong
-
Patent number: 11056432Abstract: A semiconductor package is provided. The semiconductor package includes a lower structure including an upper insulating layer and an upper pad; and a semiconductor chip provided on the lower structure and comprising a lower insulating layer and a lower pad. The lower insulating layer is in contact with and coupled to the upper insulating layer and the lower pad is in contact with and coupled to the upper pad, and a lateral side of the semiconductor chip extends between an upper side and a lower side of the semiconductor chip and comprises a recessed portion.Type: GrantFiled: June 25, 2019Date of Patent: July 6, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyuek Jae Lee, Ji Hoon Kim, Tae Hun Kim, Ji Seok Hong, Ji Hwan Hwang
-
Patent number: 11018026Abstract: A semiconductor package includes: a plurality of unit redistribution layers vertically stacked, each including: a first polymer layer having a first via hole pattern; a second polymer layer formed on the first polymer layer, and having a redistribution pattern on the first polymer layer and a second via hole pattern in the first via hole pattern; a seed layer covering sidewalls and bottom surfaces of the redistribution pattern and the second via hole pattern; a conductive via plug formed in the second via hole pattern; and a conductive redistribution line formed in the redistribution pattern; a connection terminal disposed on a bottom surface of a lowermost unit redistribution layer and electrically connected to the conductive via plug; a semiconductor device mounted on the unit redistribution layers with a conductive terminal interposed therebetween. Upper surfaces of the second polymer layer, the conductive redistribution line and the conductive via plug are substantially coplanar.Type: GrantFiled: November 29, 2019Date of Patent: May 25, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Un-Byoung Kang, Tae-Je Cho, Hyuek-Jae Lee, Cha-Jea Jo
-
Patent number: 10886255Abstract: A die stack structure may include a base die having base contact pads insulated by a base protection patterns and a flat side surface, a die stack bonded to the base die and having a plurality of component dies on the base die such that each of the component dies includes component contact pads insulated by a corresponding component protection pattern, and a residual mold unevenly arranged on a side surface of the die stack such that the component dies are attached to each other by the residual mold.Type: GrantFiled: August 6, 2019Date of Patent: January 5, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-Seok Hong, Ji-Hoon Kim, Tae-Hun Kim, Hyuek-Jae Lee, Ji-Hwan Hwang
-
Publication number: 20200144076Abstract: A method of fabricating an interposer includes: providing a carrier substrate; forming a unit redistribution layer on the carrier substrate, the unit redistribution layer including a conductive via plug and a conductive redistribution line; and removing the carrier substrate from the unit redistribution layer. The formation of the unit redistribution layer includes: forming a first photosensitive pattern layer including a first via hole pattern; forming a second photosensitive pattern layer including a second via hole pattern and a redistribution pattern on the first photosensitive pattern layer; at least partially filling insides of the first via hole pattern, the second via hole pattern, and the redistribution pattern with a conductive material; and performing planarization to make a top surface of the unit redistribution layer flat.Type: ApplicationFiled: November 29, 2019Publication date: May 7, 2020Inventors: UN-BYOUNG KANG, Tae-Je CHO, Hyuek-Jae LEE, Cha-Jea JO
-
Publication number: 20200135636Abstract: A semiconductor package is provided. The semiconductor package includes a lower structure including an upper insulating layer and an upper pad; and a semiconductor chip provided on the lower structure and comprising a lower insulating layer and a lower pad. The lower insulating layer is in contact with and coupled to the upper insulating layer and the lower pad is in contact with and coupled to the upper pad, and a lateral side of the semiconductor chip extends between an upper side and a lower side of the semiconductor chip and comprises a recessed portion.Type: ApplicationFiled: June 25, 2019Publication date: April 30, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyuek Jae LEE, Ji Hoon KIM, Tae Hun KIM, Ji Seok HONG, Ji Hwan HWANG
-
Publication number: 20200135699Abstract: A semiconductor package includes a base structure having a base pad, a first semiconductor chip on the base structure, and having a first connection pad bonded to the base pad, a first bonding structure including an base insulation layer of a base structure and a first lower insulation layer of the first semiconductor chip bonded to the base insulation layer, a second semiconductor chip on the first semiconductor chip, and having a second connection pad connected to the first through-electrode, and a second bonding structure including a first upper insulation layer of the first semiconductor chip, and a second lower insulation layer of the second semiconductor chip bonded to the first upper insulation layer, and the first upper insulation layer has a dummy insulation portion extending onto the base structure around the first semiconductor chip.Type: ApplicationFiled: October 1, 2019Publication date: April 30, 2020Inventors: Ji Hwan HWANG, Ji Hoon KIM, Ji Seok HONG, Tae Hun KIM, Hyuek Jae LEE
-
Publication number: 20200135594Abstract: A semiconductor package includes a base including a first bonding structure; and a first semiconductor chip, including a second bonding structure, the second bonding structure being coupled to the first bonding structure of the base, wherein the first bonding structure includes: a test pad; a first pad being electrically connected to the test pad; and a first insulating layer, wherein the second bonding structure includes: a second pad being electrically connected to the first pad; and a second insulating layer being in contact with the first insulating layer, and wherein at least a portion of the test pad is in contact with the second insulating layer.Type: ApplicationFiled: July 11, 2019Publication date: April 30, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyuek Jae LEE, Tae Hun KIM, Ji Hwan HWANG, Ji Hoon KIM, Ji Seok HONG
-
Publication number: 20200135698Abstract: A die stack structure may include a base die having base contact pads insulated by a base protection patterns and a flat side surface, a die stack bonded to the base die and having a plurality of component dies on the base die such that each of the component dies includes component contact pads insulated by a corresponding component protection pattern, and a residual mold unevenly arranged on a side surface of the die stack such that the component dies are attached to each other by the residual mold.Type: ApplicationFiled: August 6, 2019Publication date: April 30, 2020Inventors: Ji-Seok HONG, Ji-Hoon KIM, Tae-Hun KIM, Hyuek-Jae LEE, Ji-Hwan HWANG