Abstract: A power line layout for a semiconductor device includes a memory cell region, a plurality of wordline enable signal lines in the memory cell region, a plurality of first power lines arranged between the wordline enable signal lines in the memory cell region, and a plurality of second power lines arranged perpendicular to the first power lines in the memory cell region to form a mesh arrangement of first and second power lines.

Abstract: A semiconductor memory device and an arrangement method thereof are disclosed. The semiconductor memory device comprises column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged on a different layer from the column selecting signal lines above the memory cell array, in a perpendicular direction to the column selecting signal lines; and second local data IO signal lines arranged on a different layer from the column selecting signal lines and the word lines above the memory cell array, in the same direction as the first local data IO signal lines.

Abstract: A semiconductor memory device and an arrangement method thereof are disclosed. The semiconductor memory device comprises column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged on a different layer from the column selecting signal lines above the memory cell array, in a perpendicular direction to the column selecting signal lines; and second local data IO signal lines arranged on a different layer from the column selecting signal lines and the word lines above the memory cell array, in the same direction as the first local data IO signal lines.

Abstract: A semiconductor memory device and an arrangement method thereof are disclosed. The semiconductor memory device comprises column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged on a different layer from the column selecting signal lines above the memory cell array, in a perpendicular direction to the column selecting signal lines; and second local data IO signal lines arranged on a different layer from the column selecting signal lines and the word lines above the memory cell array, in the same direction as the first local data IO signal lines.

Abstract: An input buffer circuit achieving rail-to-rail operation maintains a uniform common mode output voltage even though an input signal having any voltage level is inputted. The input buffer circuit has a differential amplifier structure receiving two differential input signals. A first input part has a first inverter circuit into which a first differential input signal is inputted, and a second input part has a second inverter circuit into which the second differential input signal is inputted. The first inverter circuit has a first output node connected to a diode structure having an operating current twice the operating current of the first inverter circuit, and outputs a first output signal. Rail-to-rail operation is achieved, and a common mode output voltage is provided uniformly, with reduced current consumption.

Abstract: A CMOS inverter cell having a small horizontal length which is reduced by substituting metal lines for supplying data signals to gates with a connection pattern which is mounted in one end of a supply voltage area of the CMOS inverter cell and is made of the same material as the gate. Data is supplied to the gates through at least one side of the CMOS inverter cell. A single gate pattern or a plurality of different gate patterns may be used.

Abstract: A pad layout structure may include a pad and adjacent circuit areas having an electrostatic protection circuit and a data input/output circuit. The pad may be selectively connected to the adjacent circuit areas depending on the intended use of the pad.

Abstract: An input buffer circuit achieving rail-to-rail operation maintains a uniform common mode output voltage even though an input signal having any voltage level is inputted. The input buffer circuit has a differential amplifier structure (and receiving two differential input signals. A first input part has a first inverter circuit into which a first differential input signal is inputted, and a second input part has a second inverter circuit into which the second differential input signal is inputted. The first inverter circuit has a first output node connected to a diode structure having an operating current twice the operating current of the first inverter circuit, and outputs a first output signal. Rail-to-rail operation is achieved, and a common mode output voltage is provided uniformly, with reduced current consumption.

Abstract: Disclosed herein are a semiconductor method and device which are capable of reducing data write errors by rewriting last write data during a write recovery time (tWR). The semiconductor device comprises a memory cell array consisting of a plurality of repetitive cell units; a bit line amplifier for amplifying a voltage difference between a bit line voltage and a complementary bit line voltage of the memory cell array; switching devices activated by a column selection line signal for electrically connecting a data line and a complementary data line to the bit line and the complementary bit line, respectively; and a write driver for supplying a write data voltage to the data line and the complementary data line, wherein the column selection line signal is generated during a write recovery time.

Abstract: Disclosed is a differential amplifier having a high voltage gain and a stable common-mode output voltage. The differential amplifier is comprised of a signal loading circuit to regulate the amount of currents flowing through first and second signal output terminals. The signal loading circuit includes first and second loading diodes to regulate the amount of currents flowing each to the first and second output terminals from a power source voltage, and a loading source to regulate current amount flowing from the power source voltage to the second signal output terminal in response to the first signal output signal. The differential amplifier is characterized with a high voltage gain for a small signal, generating a stable common-mode output voltage against variation of a common-mode voltage of input voltages as well.

Abstract: A semiconductor memory device and an arrangement method thereof are disclosed. The semiconductor memory device comprises column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged on a different layer from the column selecting signal lines above the memory cell array, in a perpendicular direction to the column selecting signal lines; and second local data IO signal lines arranged on a different layer from the column selecting signal lines and the word lines above the memory cell array, in the same direction as the first local data IO signal lines.

Abstract: An adapter is provided link between auxiliary Satellite Digital Audio Radio Services Receiver and in-dash AM/FM car radio. The adapter proposed in this invention combines together a wireless FM communication links and a hard-wired RF link. The adapter can be easily reconfigured through user interface and implemented in two modes. The adapter structure and two modes application variety did not depend on analog or digital audio signals which have to be transmitted from SDARS receivers (Satellite Digital Audio Radio Services Receiver) to the car stereo through in-dash AM/FM radio.

Abstract: Disclosed is a wireless remote controller using a time division protocol. A satellite radio equipped with the wireless remote controller is also disclosed which performs an audio processing operation for time division multiplexing (TDM) and orthogonal frequency division multiplexing (OFDM) signals respectively transmitted from satellites and a terrestrial repeater by demodulating and digitally processing the TDM and OFDM signals. The remote controller includes a transceiver for performing a bi-directional communication through a single channel in such a manner that transmission and reception sides are sync with each other in accordance with a time division duplexing scheme, the transceiver wirelessly transmitting a command from a user, and executing a response received thereto. A Bluetooth radio modem and a commercially available inexpensive protocol can be used, so that it is possible to inexpensively provide, to the driver, the same convenience and advantages as the conventional system.

Abstract: Disclosed herein are a semiconductor method and device which are capable of reducing data write errors by rewriting last write data during a write recovery time (tWR). The semiconductor device comprises a memory cell array consisting of a plurality of repetitive cell units; a bit line amplifier for amplifying a voltage difference between a bit line voltage and a complementary bit line voltage of the memory cell array; switching devices activated by a column selection line signal for electrically connecting a data line and a complementary data line to the bit line and the complementary bit line, respectively; and a write driver for supplying a write data voltage to the data line and the complementary data line, wherein the column selection line signal is generated during a write recovery time.