Patents by Inventor Hyun-Chul Seo

Hyun-Chul Seo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220173323
    Abstract: An organic light emitting diode and an organic light emitting device containing the same are provided. The organic light emitting diode includes at least two emitting parts each of which includes independently an emitting material layer. Each of the emitting material layers includes independently an anthracene-based host having different deuterium substitution rates. The organic light emitting device includes the organic light emitting diode. Hosts with different deuterium substitution rates are introduced into each organic emitting material layer to improve luminous efficiency and luminous lifespan of the organic light emitting diode and the organic light emitting device.
    Type: Application
    Filed: December 1, 2021
    Publication date: June 2, 2022
    Inventors: Young-Jun YU, Sang-Beom KIM, Hyun-Chul CHOI, Ji-Ho BAEK, In-Bum SONG, Jeong-Dae SEO, Sun-Kap KWON
  • Publication number: 20220173324
    Abstract: An organic light emitting device that includes a substrate and an organic light emitting diode positioned on the substrate is provided. The organic light emitting diode includes a first electrode, a second electrode facing the first electrode, a first emitting material layer including a first compound and positioned between the first and second electrodes, and a second emitting material layer including a second compound and positioned between the first emitting material layer and the second electrode. Each of the first and second compounds is an anthracene derivative, and a deuteration ratio of the first compound is greater than that of the second compound.
    Type: Application
    Filed: December 1, 2021
    Publication date: June 2, 2022
    Inventors: Young-Jun YU, Sang-Beom KIM, Hyun-Chul CHOI, In-Bum SONG, Do-Han KIM, Jeong-Dae SEO, Tae-Shick KIM
  • Patent number: 11330836
    Abstract: A lyocell material for a cigarette filter and a method of manufacturing the same are disclose. The lyocell material which is biodegradable and eco-friendly can be manufactured by crimping lyocell multifilaments to obtain a crimped tow.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: May 17, 2022
    Inventors: Jong Cheol Jeong, Woo Chul Kim, Sang Woo Jin, Burm Ho Yang, Man Seok Seo, Kyung Joon Lee, Hyun Suk Cho, Jong Yeol Kim
  • Publication number: 20220067125
    Abstract: A method of distributing a amount of issuance of digital content includes: determining the amount of issuance corresponding to a certificate of right to use digital content; generating blocks corresponding to the amount of issuance in accordance with the certificate of right to use the digital content and adding the blocks to a block chain system; generating an authentication certificate including a key value of the generated blocks in connection with the certificate of right to use the digital content; receiving a purchase request for the certificate of right to use of the digital content from a first user terminal; transmitting the digital content to the first user terminal such that the digital content is stored in a content folder of the first user terminal; transmitting a first authentication certificate corresponding to a remaining amount among the amount of issuance to the first user terminal, and storing the first authentication certificate in connection with the certificate of right to use the digita
    Type: Application
    Filed: October 8, 2021
    Publication date: March 3, 2022
    Inventor: Hyun Chul SEO
  • Publication number: 20220013469
    Abstract: A semiconductor device includes: a semiconductor wafer with a chip region and an edge region and with an identification mark formed on one surface of the semiconductor wafer in the edge region; conductive connectors formed on the one surface of the semiconductor wafer in the chip region; and dummy conductive connectors formed on the one surface of the semiconductor wafer in the edge region, wherein the dummy conductive connectors do not overlap with the identification mark.
    Type: Application
    Filed: September 11, 2020
    Publication date: January 13, 2022
    Applicant: SK hynix Inc.
    Inventor: Hyun Chul SEO
  • Publication number: 20220013418
    Abstract: A semiconductor wafer includes a first chip region and a second chip region spaced apart from each other by a scribe lane region. The semiconductor wafer also includes a test pad disposed in the scribe lane region. The semiconductor wafer additionally includes a protective layer partially covering the first chip region, the second chip region, and the scribe lane region, wherein the protective layer covers a portion of the test pad adjacent to the first chip region and leaves a remaining portion of the first test pad exposed.
    Type: Application
    Filed: October 27, 2020
    Publication date: January 13, 2022
    Applicant: SK hynix Inc.
    Inventor: Hyun Chul SEO
  • Publication number: 20220013419
    Abstract: A semiconductor package includes a semiconductor chip with a normal connection electrode and a measurement connection electrode, formed on a first surface, and a substrate with a normal substrate pad, connected to the normal connection electrode, and a measurement substrate pad, connected to the measurement connection electrode. The normal substrate pad and the measurement substrate pad are formed on a surface that faces the first surface. The measurement connection electrode includes first and second edge measurement connection electrodes and first and second center measurement connection electrodes. The measurement substrate pad includes a center measurement substrate pad, a first edge measurement substrate pad, and a second edge measurement substrate pad.
    Type: Application
    Filed: November 12, 2020
    Publication date: January 13, 2022
    Applicant: SK hynix Inc.
    Inventor: Hyun Chul SEO
  • Patent number: 11217544
    Abstract: A semiconductor package includes: a package substrate; a first semiconductor chip disposed over the package substrate and having a center region and an edge region; and a package redistribution layer disposed over the first semiconductor chip, wherein the first semiconductor chip comprises: a lower structure; a redistribution conductive layer disposed over the lower structure and electrically connected to the lower structure, the redistribution conductive layer including a redistribution pad disposed in the center region; and a protective layer covering the lower structure and the redistribution conductive layer, and having an opening exposing the redistribution pad, wherein the package redistribution layer comprises: a package redistribution conductive layer connected to the redistribution pad and extending to the edge region, the package redistribution conductive layer including a package redistribution pad disposed in the edge region, and, wherein, in the edge region, the redistribution conductive layer is
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: January 4, 2022
    Assignee: SK hynix Inc.
    Inventors: Jong Hyun Kim, Seung Hwan Kim, Hyun Chul Seo, Ki Young Kim
  • Publication number: 20210366853
    Abstract: A semiconductor package includes: a package substrate; a first semiconductor chip disposed over the package substrate and having a center region and an edge region; and a package redistribution layer disposed over the first semiconductor chip, wherein the first semiconductor chip comprises: a lower structure; a redistribution conductive layer disposed over the lower structure and electrically connected to the lower structure, the redistribution conductive layer including a redistribution pad disposed in the center region; and a protective layer covering the lower structure and the redistribution conductive layer, and having an opening exposing the redistribution pad, wherein the package redistribution layer comprises: a package redistribution conductive layer connected to the redistribution pad and extending to the edge region, the package redistribution conductive layer including a package redistribution pad disposed in the edge region, and, wherein, in the edge region, the redistribution conductive layer is
    Type: Application
    Filed: August 25, 2020
    Publication date: November 25, 2021
    Applicant: SK hynix Inc.
    Inventors: Jong Hyun KIM, Seung Hwan KIM, Hyun Chul SEO, Ki Young KIM
  • Patent number: 11088117
    Abstract: Disclosed is a semiconductor package. The semiconductor package includes a substrate including an opening, a first semiconductor chip, disposed on the substrate, including a plurality of first chip pads exposed through the opening, a second semiconductor chip, disposed on the first semiconductor chip to partially overlap with the first semiconductor chip, including a plurality of second chip pads, aligned with the opening, and a redistribution layer formed on a surface on which the second chip pads of the second semiconductor chip are disposed. One or more of the second chip pads overlaps with the first semiconductor chip and is covered by the first semiconductor chip and with the remaining pads of the second chip pads being exposed through the opening. The redistribution layer includes redistribution pads, exposed through the opening, and includes redistribution lines, configured to connect the one or more of the second chip pads to the redistribution pads.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: August 10, 2021
    Assignee: SK hynix Inc.
    Inventors: Hyun-Chul Seo, Jun-Sik Kim
  • Publication number: 20210202415
    Abstract: A semiconductor device includes: a lower structure; a redistribution insulating layer disposed over the lower structure; a redistribution conductive layer disposed over the redistribution insulating layer and electrically connected to a part of the lower structure, the redistribution conductive layer including a redistribution pad; and a protective layer covering the redistribution insulating layer and the redistribution conductive layer while leaving the redistribution pad exposed. The redistribution conductive layer includes a trench disposed adjacent to the redistribution pad, and a part of the protective layer fills the trench.
    Type: Application
    Filed: August 13, 2020
    Publication date: July 1, 2021
    Applicant: SK hynix Inc.
    Inventors: Seung Hwan KIM, Hyun Chul SEO, Hyeong Seok CHOI, Shin Young PARK
  • Patent number: 10991598
    Abstract: A method of fabricating a semiconductor package may include forming a plating layer on a surface of a substrate body. A circuit resist pattern and a monitoring resist pattern may be formed on the plating layer, and the plating layer may be etched using the circuit resist pattern and the monitoring resist pattern as etch masks, thereby forming circuit patterns and sub-patterns of a monitoring pattern. A residual rate of the circuit patterns may be monitored by inspecting the number of the sub-patterns of the monitoring pattern remaining on the substrate body after an etch process for forming the circuit patterns and the sub-patterns of the monitoring pattern. A semiconductor chip may be bonded to the circuit patterns using inner connectors.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: April 27, 2021
    Assignee: SK hynix Inc.
    Inventors: Hyeong Seok Choi, Hyun Chul Seo, Seang Hwan Kim
  • Publication number: 20210013180
    Abstract: Disclosed is a semiconductor package. The semiconductor package includes a substrate including an opening, a first semiconductor chip, disposed on the substrate, including a plurality of first chip pads exposed through the opening, a second semiconductor chip, disposed on the first semiconductor chip to partially overlap with the first semiconductor chip, including a plurality of second chip pads, aligned with the opening, and a redistribution layer formed on a surface on which the second chip pads of the second semiconductor chip are disposed. One or more of the second chip pads overlaps with the first semiconductor chip and is covered by the first semiconductor chip and with the remaining pads of the second chip pads being exposed through the opening. The redistribution layer includes redistribution pads, exposed through the opening, and includes redistribution lines, configured to connect the one or more of the second chip pads to the redistribution pads.
    Type: Application
    Filed: December 10, 2019
    Publication date: January 14, 2021
    Applicant: SK hynix Inc.
    Inventors: Hyun-Chul SEO, Jun-Sik KIM
  • Publication number: 20200168473
    Abstract: A method of fabricating a semiconductor package may include forming a plating layer on a surface of a substrate body. A circuit resist pattern and a monitoring resist pattern may be formed on the plating layer, and the plating layer may be etched using the circuit resist pattern and the monitoring resist pattern as etch masks, thereby forming circuit patterns and sub-patterns of a monitoring pattern. A residual rate of the circuit patterns may be monitored by inspecting the number of the sub-patterns of the monitoring pattern remaining on the substrate body after an etch process for forming the circuit patterns and the sub-patterns of the monitoring pattern. A semiconductor chip may be bonded to the circuit patterns using inner connectors.
    Type: Application
    Filed: June 21, 2019
    Publication date: May 28, 2020
    Applicant: SK hynix Inc.
    Inventors: Hyeong Seok CHOI, Hyun Chul SEO, Seang Hwan KIM
  • Patent number: 10460771
    Abstract: A semiconductor chip module includes a chip unit including first and second semiconductor chips formed over a single body to be adjacent in a first direction with a scribe line region interposed therebetween, and having a first surface over which bonding pads of the first and second semiconductor chips are positioned; redistribution lines formed over the first surface, having one set of ends which are respectively electrically coupled to the bonding pads, and extending in a direction oblique to the first direction toward the scribe line region; and redistribution pads disposed over the first surface, and electrically coupled with another set of ends of the redistribution lines.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: October 29, 2019
    Assignee: SK hynix Inc.
    Inventors: Hyun Chul Seo, Jun Sik Kim
  • Patent number: 10366727
    Abstract: A semiconductor chip module includes a chip unit including first and second semiconductor chips formed over a single body to be adjacent in a first direction with a scribe line region interposed therebetween, and having a first surface over which bonding pads of the first and second semiconductor chips are positioned; redistribution lines formed over the first surface, having one set of ends which are respectively electrically coupled to the bonding pads, and extending in a direction oblique to the first direction toward the scribe line region; and redistribution pads disposed over the first surface, and electrically coupled with another set of ends of the redistribution lines.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: July 30, 2019
    Assignee: SK hynix Inc.
    Inventors: Hyun Chul Seo, Jun Sik Kim
  • Publication number: 20190164578
    Abstract: A semiconductor chip module includes a chip unit including first and second semiconductor chips formed over a single body to be adjacent in a first direction with a scribe line region interposed therebetween, and having a first surface over which bonding pads of the first and second semiconductor chips are positioned; redistribution lines formed over the first surface, having one set of ends which are respectively electrically coupled to the bonding pads, and extending in a direction oblique to the first direction toward the scribe line region; and redistribution pads disposed over the first surface, and electrically coupled with another set of ends of the redistribution lines.
    Type: Application
    Filed: February 1, 2019
    Publication date: May 30, 2019
    Applicant: SK hynix Inc.
    Inventors: Hyun Chul SEO, Jun Sik Kim
  • Patent number: 9666240
    Abstract: A semiconductor device includes, a semiconductor chip having a first surface over which bonding pads are positioned, a second surface which faces away from the first surface, and a plurality of signal lines formed over the first surface, extending in a first direction; a plurality of redistribution lines formed over the first surface, having one set of ends electrically coupled to the bonding pads of the semiconductor chip, and extending in a direction oblique to the first direction; and a plurality of redistribution pads disposed over the first surface, and electrically coupled with an other set of ends of the redistribution lines which face away from the one set of ends.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: May 30, 2017
    Assignee: SK hynix Inc.
    Inventor: Hyun Chul Seo
  • Publication number: 20170110160
    Abstract: A semiconductor chip module includes a chip unit including first and second semiconductor chips formed over a single body to be adjacent in a first direction with a scribe line region interposed therebetween, and having a first surface over which bonding pads of the first and second semiconductor chips are positioned; redistribution lines formed over the first surface, having one set of ends which are respectively electrically coupled to the bonding pads, and extending in a direction oblique to the first direction toward the scribe line region; and redistribution pads disposed over the first surface, and electrically coupled with another set of ends of the redistribution lines.
    Type: Application
    Filed: February 23, 2016
    Publication date: April 20, 2017
    Inventors: Hyun Chul SEO, Jun Sik KIM
  • Publication number: 20170110161
    Abstract: A semiconductor device includes, a semiconductor chip having a first surface over which bonding pads are positioned, a second surface which faces away from the first surface, and a plurality of signal lines formed over the first surface, extending in a first direction; a plurality of redistribution lines formed over the first surface, having one set of ends electrically coupled to the bonding pads of the semiconductor chip, and extending in a direction oblique to the first direction; and a plurality of redistribution pads disposed over the first surface, and electrically coupled with an other set of ends of the redistribution lines which face away from the one set of ends.
    Type: Application
    Filed: February 24, 2016
    Publication date: April 20, 2017
    Inventor: Hyun Chul SEO