Abstract: A semiconductor chip includes a body part having a front surface and a rear surface, a plurality of through electrodes penetrating the body part and arranged in a first direction in an array region, a plurality of front surface connection electrodes respectively coupled to the through electrodes over the front surface of the body part, and a plurality of rear surface connection electrodes respectively coupled to the through electrodes over the rear surface of the body part. The array region includes a central region and edge regions positioned on both sides of the central region in the first direction. A center of the front surface connection electrode and a center of the rear surface connection electrode that are positioned in each of the edge regions are positioned at a distance farther from the central region than a center of the corresponding through electrode.

Abstract: A method of manufacturing a semiconductor package includes mounting a first semiconductor chip and a second semiconductor chip on a substrate, forming a first film on a top surface of the first semiconductor chip, and loading the first semiconductor chip and the second semiconductor chip mounted on the substrate between a lower mold frame and an upper mold frame. The method further includes providing a molding material between the lower mold frame and the upper mold frame, removing the lower mold frame and the upper mold frame, and removing the first film on the top surface of the first semiconductor chip to expose the top surface of the first semiconductor chip.

Abstract: A semiconductor chip includes a body part having a front surface and a rear surface, a plurality of through electrodes penetrating the body part and arranged in a first direction in an array region, a plurality of front surface connection electrodes respectively coupled to the through electrodes over the front surface of the body part, and a plurality of rear surface connection electrodes respectively coupled to the through electrodes over the rear surface of the body part. The array region includes a central region and edge regions positioned on both sides of the central region in the first direction. A center of the front surface connection electrode and a center of the rear surface connection electrode that are positioned in each of the edge regions are positioned at a distance farther from the central region than a center of the corresponding through electrode.

Abstract: A semiconductor package includes a semiconductor chip and a package substrate. The semiconductor chip is mounted on the package substrate. The package substrate includes a dielectric layer through which a vent hole penetrates, trace patterns disposed on the dielectric layer, and a protecting block disposed between the trace patterns and the vent hole.

Abstract: A semiconductor chip includes a chip body, a redistribution layer pattern disposed on a surface of the chip body, an alignment mark pattern disposed to be spaced apart from the redistribution layer pattern on the surface of the chip body, a first insulating pattern disposed to contact a side surface of the redistribution layer pattern and a side surface of the alignment mark pattern on the surface of the chip body, a second insulating pattern disposed on the redistribution layer pattern to protect the redistribution layer pattern, and an alignment mark protection pattern disposed on the alignment mark pattern.

Abstract: A semiconductor package includes: a substrate; a first semiconductor chip positioned over the substrate and electrically connected to the substrate; a second semiconductor chip stack positioned over the first semiconductor chip and including a plurality of second semiconductor chips that are stacked in a vertical direction while being electrically connected to the first semiconductor chip; and a dummy third semiconductor chip positioned over the second semiconductor chip stack, wherein a third height of a third bonding structure coupling the third semiconductor chip to an uppermost second semiconductor chip among the second semiconductor chips is greater than a second height of a second bonding structure coupling one among the second semiconductor chips to an another one among the second semiconductor chips positioned directly therebelow or the first semiconductor chip positioned directly therebelow.

Abstract: A method of manufacturing a semiconductor package includes mounting a first semiconductor chip and a second semiconductor chip on a substrate, forming a first film on a top surface of the first semiconductor chip, and loading the first semiconductor chip and the second semiconductor chip mounted on the substrate between a lower mold frame and an upper mold frame. The method further includes providing a molding material between the lower mold frame and the upper mold frame, removing the lower mold frame and the upper mold frame, and removing the first film on the top surface of the first semiconductor chip to expose the top surface of the first semiconductor chip.

Abstract: A semiconductor package includes a semiconductor chip and a package substrate. The semiconductor chip is mounted on the package substrate. The package substrate includes a dielectric layer through which a vent hole penetrates, trace patterns disposed on the dielectric layer, and a protecting block disposed between the trace patterns and the vent hole.

Abstract: A semiconductor device includes a first redistribution layer pattern, a second redistribution layer pattern, and a recognition mark. The first redistribution layer pattern is formed on a semiconductor substrate. The second redistribution layer pattern, with a bonding pad portion, is disposed on the first redistribution layer pattern. Furthermore, the recognition mark is formed on the first redistribution layer pattern to indicate a position of the bonding pad portion.

Abstract: A semiconductor device includes: a lower structure; a redistribution insulating layer disposed over the lower structure; a redistribution conductive layer disposed over the redistribution insulating layer and electrically connected to a part of the lower structure, the redistribution conductive layer including a redistribution pad; and a protective layer covering the redistribution insulating layer and the redistribution conductive layer while leaving the redistribution pad exposed. The redistribution conductive layer includes a trench disposed adjacent to the redistribution pad, and a part of the protective layer fills the trench.

Abstract: A semiconductor package includes a semiconductor chip with a normal connection electrode and a measurement connection electrode, formed on a first surface, and a substrate with a normal substrate pad, connected to the normal connection electrode, and a measurement substrate pad, connected to the measurement connection electrode. The normal substrate pad and the measurement substrate pad are formed on a surface that faces the first surface. The measurement connection electrode includes first and second edge measurement connection electrodes and first and second center measurement connection electrodes. The measurement substrate pad includes a center measurement substrate pad, a first edge measurement substrate pad, and a second edge measurement substrate pad.

Abstract: A semiconductor wafer includes a first chip region and a second chip region spaced apart from each other by a scribe lane region. The semiconductor wafer also includes a test pad disposed in the scribe lane region. The semiconductor wafer additionally includes a protective layer partially covering the first chip region, the second chip region, and the scribe lane region, wherein the protective layer covers a portion of the test pad adjacent to the first chip region and leaves a remaining portion of the first test pad exposed.

Abstract: A semiconductor chip includes a body part having a front surface and a rear surface, a plurality of through electrodes penetrating the body part and arranged in a first direction in an array region, a plurality of front surface connection electrodes respectively coupled to the through electrodes over the front surface of the body part, and a plurality of rear surface connection electrodes respectively coupled to the through electrodes over the rear surface of the body part. The array region includes a central region and edge regions positioned on both sides of the central region in the first direction. A center of the front surface connection electrode and a center of the rear surface connection electrode that are positioned in each of the edge regions are positioned at a distance farther from the central region than a center of the corresponding through electrode.

Abstract: A method of distributing a amount of issuance of digital content includes: determining the amount of issuance corresponding to a certificate of right to use digital content; generating blocks corresponding to the amount of issuance in accordance with the certificate of right to use the digital content and adding the blocks to a block chain system; generating an authentication certificate including a key value of the generated blocks in connection with the certificate of right to use the digital content; receiving a purchase request for the certificate of right to use of the digital content from a first user terminal; transmitting the digital content to the first user terminal such that the digital content is stored in a content folder of the first user terminal; transmitting a first authentication certificate corresponding to a remaining amount among the amount of issuance to the first user terminal, and storing the first authentication certificate in connection with the certificate of right to use the digita

Abstract: A semiconductor device includes: a semiconductor wafer with a chip region and an edge region and with an identification mark formed on one surface of the semiconductor wafer in the edge region; conductive connectors formed on the one surface of the semiconductor wafer in the chip region; and dummy conductive connectors formed on the one surface of the semiconductor wafer in the edge region, wherein the dummy conductive connectors do not overlap with the identification mark.

Abstract: A semiconductor wafer includes a first chip region and a second chip region spaced apart from each other by a scribe lane region. The semiconductor wafer also includes a test pad disposed in the scribe lane region. The semiconductor wafer additionally includes a protective layer partially covering the first chip region, the second chip region, and the scribe lane region, wherein the protective layer covers a portion of the test pad adjacent to the first chip region and leaves a remaining portion of the first test pad exposed.

Abstract: A semiconductor package includes a semiconductor chip with a normal connection electrode and a measurement connection electrode, formed on a first surface, and a substrate with a normal substrate pad, connected to the normal connection electrode, and a measurement substrate pad, connected to the measurement connection electrode. The normal substrate pad and the measurement substrate pad are formed on a surface that faces the first surface. The measurement connection electrode includes first and second edge measurement connection electrodes and first and second center measurement connection electrodes. The measurement substrate pad includes a center measurement substrate pad, a first edge measurement substrate pad, and a second edge measurement substrate pad.

Abstract: A semiconductor package includes: a package substrate; a first semiconductor chip disposed over the package substrate and having a center region and an edge region; and a package redistribution layer disposed over the first semiconductor chip, wherein the first semiconductor chip comprises: a lower structure; a redistribution conductive layer disposed over the lower structure and electrically connected to the lower structure, the redistribution conductive layer including a redistribution pad disposed in the center region; and a protective layer covering the lower structure and the redistribution conductive layer, and having an opening exposing the redistribution pad, wherein the package redistribution layer comprises: a package redistribution conductive layer connected to the redistribution pad and extending to the edge region, the package redistribution conductive layer including a package redistribution pad disposed in the edge region, and, wherein, in the edge region, the redistribution conductive layer is

Abstract: A semiconductor package includes: a package substrate; a first semiconductor chip disposed over the package substrate and having a center region and an edge region; and a package redistribution layer disposed over the first semiconductor chip, wherein the first semiconductor chip comprises: a lower structure; a redistribution conductive layer disposed over the lower structure and electrically connected to the lower structure, the redistribution conductive layer including a redistribution pad disposed in the center region; and a protective layer covering the lower structure and the redistribution conductive layer, and having an opening exposing the redistribution pad, wherein the package redistribution layer comprises: a package redistribution conductive layer connected to the redistribution pad and extending to the edge region, the package redistribution conductive layer including a package redistribution pad disposed in the edge region, and, wherein, in the edge region, the redistribution conductive layer is

Abstract: Disclosed is a semiconductor package. The semiconductor package includes a substrate including an opening, a first semiconductor chip, disposed on the substrate, including a plurality of first chip pads exposed through the opening, a second semiconductor chip, disposed on the first semiconductor chip to partially overlap with the first semiconductor chip, including a plurality of second chip pads, aligned with the opening, and a redistribution layer formed on a surface on which the second chip pads of the second semiconductor chip are disposed. One or more of the second chip pads overlaps with the first semiconductor chip and is covered by the first semiconductor chip and with the remaining pads of the second chip pads being exposed through the opening. The redistribution layer includes redistribution pads, exposed through the opening, and includes redistribution lines, configured to connect the one or more of the second chip pads to the redistribution pads.