Patents by Inventor Hyun-Kyu Yu

Hyun-Kyu Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6992366
    Abstract: Disclosed is a stacked variable inductors manufactured by stacking M (M?2) metal layers on a semiconductor substrate, and provides stacked variable inductors comprising, 1 to N inductors continuously connected in serial, wherein each of said inductors is formed on N (N?M) metal layers that are different each other; first and second ports each connected to the highest positioned inductor and to the lowest positioned inductor among said 1 to N inductors; and at least one MOSFET, and wherein one terminal of at least one MOSFET is connected to one of the first and second ports, and the other one is connected to one of adjacent terminals connected in serial between 1 to N inductors.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: January 31, 2006
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Cheon Soo Kim, Pil Jae Park, Mun Yang Park, Hyun Kyu Yu
  • Patent number: 6940350
    Abstract: An amplifier including an amplifier transistor that operates in an active region has main current flowing therethrough according to input voltage, and a linear transistor that is driven by offset positive-polarity input voltage to operate in a linear region and has auxiliary current flowing therethrough. The main current and auxiliary current are added to become output current. The offset positive-polarity voltage corresponds to the sum of AC component of the input voltage and an offset DC voltage. Here, a transistor stacked on the linear transistor is coupled to the amplifier transistor to secure the linear region operation of the linear transistor. The stacked transistor is driven by a voltage having polarity opposite to that of the input voltage.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: September 6, 2005
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Yong-Sik Youn, Hyun-Kyu Yu, Mun-Yang Park
  • Patent number: 6831497
    Abstract: An active quadrature signal generator produces poly-phase quadrature signals necessary in high frequency transmit and receive elements of a communication system. The quadrature signals are produced using the phase difference between a load representing a low-pass filter characteristic and a load representing a high-pass filter characteristic and the quadrature signal is then used in the differential structure to produce amplified signal having 4 quadrature phases. The device can reduce a loss characteristic of the signal and additional power consumption for compensating for it in a common poly-phase quadrature filter having only conventional resistors and capacitor.
    Type: Grant
    Filed: June 24, 2002
    Date of Patent: December 14, 2004
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Kwang Jin Koh, Hyun Kyu Yu
  • Publication number: 20040140528
    Abstract: Disclosed is a stacked variable inductors manufactured by stacking M (M≧2) metal layers on a semiconductor substrate, and provides stacked variable inductors comprising, 1 to N inductors continuously connected in serial, wherein each of said inductors is formed on N (N≦M) metal layers that are different each other; first and second ports each connected to the highest positioned inductor and to the lowest positioned inductor among said 1 to N inductors; and at least one MOSFET, and wherein one terminal of at least one MOSFET is connected to one of the first and second ports, and the other one is connected to one of adjacent terminals connected in serial between 1 to N inductors.
    Type: Application
    Filed: September 29, 2003
    Publication date: July 22, 2004
    Inventors: Cheon Soo Kim, Pil Jae Park, Mun Yang Park, Hyun Kyu Yu
  • Publication number: 20040119538
    Abstract: An amplifier including an amplifier transistor that operates in an active region has main current flowing therethrough according to input voltage, and a linear transistor that is driven by offset positive-polarity input voltage to operate in a linear region and has auxiliary current flowing therethrough. The main current and auxiliary current are added to become output current. The offset positive-polarity voltage corresponds to the sum of AC component of the input voltage and an offset DC voltage. Here, a transistor stacked on the linear transistor is coupled to the amplifier transistor to secure the linear region operation of the linear transistor. The stacked transistor is driven by a voltage having polarity opposite to that of the input voltage.
    Type: Application
    Filed: July 11, 2003
    Publication date: June 24, 2004
    Inventors: Yong-Sik Youn, Hyun-Kyu Yu, Mun-Yang Park
  • Patent number: 6668035
    Abstract: The present invention relates to a structure of a delta-sigma fractional type divider. The divider structure adds an external input value and an output value of a delta-sigma modulator to modulate a value of a swallow counter. Therefore, the present invention can provide a delta-sigma fractional type divider the structure is simple and that can obtain an effect of a structure of a delta sigma mode while having a wide-band frequency mixing capability.
    Type: Grant
    Filed: June 24, 2002
    Date of Patent: December 23, 2003
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Seon Ho Han, Jang Hong Choi, Jae Hong Jang, Hyun Kyu Yu
  • Patent number: 6620667
    Abstract: A method of forming an HF power device. The method includes forming a semiconductor layer as a first conductive type on a semiconductor substrate; etching the semiconductor layer forming a first trench; doping an impurity in the neighborhood of the first trench forming a first impurity layer; burying a conduction film into the first trench; etching the semiconductor layer forming a second trench; forming a field oxide film buried into the second trench; forming a gate electrode on a surface of the semiconductor layer; forming a source on the surface of the semiconductor layer; forming a drain area on the surface of the semiconductor layer; forming an LLD area on the surface of the semiconductor layer between the drain area and the gate electrode; forming a first metal electrode; and forming a second metal electrode electrically connected to the LDD area.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: September 16, 2003
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Cheon-Soo Kim, Hyun-Kyu Yu, Nam Hwang, Jung-Woo Park
  • Patent number: 6615398
    Abstract: The present invention relates to a ROM division method for reducing the size of a ROM in a direct digital frequency synthesizer (DDFS), which is used to synthesize a frequency in a communication system requiring fast frequency conversion. A ROM consuming most energy in the system, a modified Nicholas architecture is brought forth to reduce the size of ROM. In this modified Nicholas architecture, a ROM is divided into coarse ROM and fine ROM to convert phase to sine value. The present invention divides the coarse ROM and the fine ROM into quantized ROM and error ROM respectively. Then, value stored in each ROM is segmented in certain intervals and the minimum quantized value in each of the section is stored in the quantized ROM, while the difference between the original ROM value and the quantized ROM value is stored in the error ROM. This way, the size of a ROM can be reduced. Phase value inputted in a DDFS, a sine value is calculated by adding the four ROM values, i.e.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: September 2, 2003
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hyun Kyu Yu, Seon-Ho Han, Mun Yang Park, Seong-Do Kim, Yong-Sik Youn, Lee-Sup Kim, Ki-Hyuk Sung, Byung-Do Yang, Young-Jun Kim
  • Patent number: 6605996
    Abstract: An automatically gain controllable linear differential amplifier using a variable degeneration resistor is disclosed. The linear differential amplifier includes an input end, a bias current source, a load unit, a first MOS transistor and a second MOS transistor. The linear differential amplifiers of the present invention can control an amplifying gain according to an input signal and improve linearity IIP3 without needing additional power consumption caused by improving the linearity. The automatically gain controllable linear differential amplifier uses NMOS/PMOS transistor so an integration process of the amplifier can be implemented more conveniently and efficiently.
    Type: Grant
    Filed: December 31, 2001
    Date of Patent: August 12, 2003
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hyun Kyu Yu, Sang-Gug Lee, Mun Yang Park, Seong-Do Kim, Yong-Sik Youn, Seon-Ho Han, Nam-Soo Kim
  • Publication number: 20030134611
    Abstract: The present invention relates to a local oscillator balun using an inverting circuit. The local oscillator balun using an inverting circuit comprises a complementary output converting circuit for amplifying a weak signal as a single signal from a local oscillator to produce two signals; a differential amplification circuit for producing two signals having a given amplitude from the two signals of said complementary output converting circuit; and an inverting circuit for inverting the two signals of the differential amplification circuit. Thus, a complementary signal having the maximum amplification and small phase difference can be produced. Therefore, the present invention can implement the maximum gain and small local oscillating leakage of the frequency mixer in a Gilbert type high frequency double balance frequency mixer.
    Type: Application
    Filed: June 24, 2002
    Publication date: July 17, 2003
    Inventors: Mun Yang Park, Seong Do Kim, Hyun Kyu Yu, Kyung Soo Kim
  • Publication number: 20030117200
    Abstract: The present invention relates to an apparatus for producing poly-phase quadrature signals necessary in the communication circuit and correcting the phase and amplitude errors. The apparatus uses a filter having high-pass and low-pass characteristics as a load of a transistor to amplify the signals and also produces quadrature phase using phase shift characteristic included in respective filters. Further, the present invention produces poly-phase quadrature signals using it as a differential structure and uses respective filter loads as a variable capacitor or a variable resistor to vary the phase and amplitude of the quadrature signal. Therefore, the present invention can reduce the loss of the signal in a common poly-phase quadrature filter having only resistors and capacitor, and additional power consumption for compensating for it.
    Type: Application
    Filed: June 24, 2002
    Publication date: June 26, 2003
    Inventors: Kwang Jin Koh, Hyun Kyu Yu
  • Publication number: 20030108143
    Abstract: The present invention relates to a structure of a delta-sigma factional divider. The divider structure adds an external input value and an output value of a delta-sigma modulator to modulate a value of a swallow counter. Therefore, the present invention can provide a delta-sigma factional divider the structure is simple and that can obtain an effect of a delta sigma mode while having a wide-band frequency mixing capability.
    Type: Application
    Filed: June 24, 2002
    Publication date: June 12, 2003
    Inventors: Seon Ho Han, Jang Hong Choi, Jae Hong Jang, Hyun Kyu Yu
  • Publication number: 20030102916
    Abstract: An automatically gain controllable linear differential amplifier using a variable degeneration resistor is disclosed. The linear differential amplifier includes an input end, a bias current source, a load unit, a first MOS transistor and a second MOS transistor. The linear differential amplifiers of the present invention can control an amplifying gain according to an input signal and improve linearity IIP3 without needing additional power consumption caused by improving the linearity The automatically gain controllable linear differential amplifier uses NMOS/PMOS transistor so an integration process of the amplifier can be implemented more conveniently and efficiently.
    Type: Application
    Filed: December 31, 2001
    Publication date: June 5, 2003
    Inventors: Hyun Kyu Yu, Sang-Gug Lee, Mun Yang Park, Seong-Do Kim, Yong-Sik Youn, Seon-Ho Han, Nam-Soo Kim
  • Publication number: 20030090339
    Abstract: The present invention relates to an integrated filter circuit for digitally controlling characteristics of inductor and capacitor to thereby produce a controlled resonant frequency. The integrated circuit includes a number of inductors being connected in series between a high frequency input node and a high frequency output node, a plurality of capacitors each connected to a connection node of said each inductors, a plurality of switches, each connected between each capacitor and a ground and a feedback control unit for controlling the switches by sensing an output signal from the high frequency output node to thereby selectively couple each capacitor to the ground through a selected switches based on the sensed output signal.
    Type: Application
    Filed: December 28, 2001
    Publication date: May 15, 2003
    Inventors: Hyun Kyu Yu, Seon-Ho Han, Mun Yang Park, Seong-Do Kim, Piljae Park, Nam-Soo Kim, Cheon Soo Kim, Yong-Sik Youn
  • Publication number: 20030036373
    Abstract: The present invention relates to a frequency mixer utilized in a transceiver of radio frequency band. The frequency mixer for a radio frequency transceiver, includes two NMOS transistors, which are commonly connected, for generating a mixed signal combined with even harmonics, wherein a first end of the NMOS transistors is input a radio frequency signal, a second end of the NMOS transistors outputs the mixed signal, and gates of the NMOS transistors receive differential signals of local oscillator. The frequency mixer needs only half local oscillation frequency and a fundamental frequency of local oscillator is not presented. Therefore, the present invention can prevent generation of DC Voltage offset and also reduce frequency of local oscillator by half when it is utilized in a heterodyne transceiver.
    Type: Application
    Filed: December 27, 2001
    Publication date: February 20, 2003
    Inventors: Hyun Kyu Yu, Nam-Soo Kim, Yong-Sik Youn, Pil Jae Park
  • Publication number: 20030014721
    Abstract: The present invention relates to a ROM division method for reducing the size of a ROM in a direct digital frequency synthesizer (DDFS), which is used to synthesize a frequency in a communication system requiring fast frequency conversion. A ROM consuming most energy in the system, a modified Nicholas architecture is brought forth to reduce the size of ROM. In this modified Nicholas architecture, a ROM is divided into coarse ROM and fine ROM to convert phase to sine value. The present invention divides the coarse ROM and the fine ROM into quantized ROM and error ROM respectively. Then, value stored in each ROM is segmented in certain intervals and the minimum quantized value in each of the section is stored in the quantized ROM, while the difference between the original ROM value and the quantized ROM value is stored in the error ROM. This way, the size of a ROM can be reduced. Phase value inputted in a DDFS, a sine value is calculated by adding the four ROM values, i.e.
    Type: Application
    Filed: December 18, 2001
    Publication date: January 16, 2003
    Inventors: Hyun Kyu Yu, Seon-Ho Han, Mun Yang Park, Seong-Do Kim, Yong-Sik Youn, Lee-Sup Kim, Ki-Hyuk Sung, Byung-Do Yang, Young-Jun Kim
  • Patent number: 6473595
    Abstract: The RF active balun circuit for improving a small-signal linearity in a power amplifying circuit of a CDMA system is provided under the construction of a signal amplifier driven by exterior individual direct current gate power VGG1, VGG2, for receiving a communication input signal AC-In and performing a cascode amplification at a normal operation point where a feedback third-order distortion signal becomes large; a distortion signal generator driven by exterior direct current gate power VGG3 different from the above power, for generating the communication input signal AC-In as the third-order distortion signal by nonlinearity of an active element to cancel the third-order distortion signal amplified in the signal amplifier; and an insulator provided for an insulation from a exterior driving power VGG3 applied to the distortion signal generator, thereby maintaining the small size, lower power and high efficient terminal characteristics by using a gain based on gate voltage of FET and the nonlinearity character
    Type: Grant
    Filed: November 10, 1999
    Date of Patent: October 29, 2002
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Chung Hwan Kim, Cheon Soo Kim, Hyun Kyu Yu, Min Park, Dae Yong Kim
  • Publication number: 20020151124
    Abstract: An HF power device in an HF transistor includes a semiconductor layer as a first conductive type, a field area formed in a trench structure on one side of the semiconductor layer, gate electrode formed on a given surface of the semiconductor layer, a channel layer as a second conductive type laterally diffused from the field area to a width containing both sides of the gate electrode, and formed on the surface of the semiconductor layer, a source area as the second conductive type formed within the channel layer between one side of the gate electrode and the field area, a drain area as the second conductive type formed on the surface of the semiconductor layer with a given interval from another side of the gate electrode, a sinker as the first conductive type provided as a column shape of a trench structure for dividing into two source areas by a piercing through the source area, and connected to the semiconductor layer, an LDD area as the second conductive type formed on the surface of the semiconductor laye
    Type: Application
    Filed: May 31, 2002
    Publication date: October 17, 2002
    Inventors: Cheon-Soo Kim, Hyun-Kyu Yu, Nam Hwang, Jung-Woo Park
  • Patent number: 6395637
    Abstract: The present invention relates to a method for fabricating an inductor and, more particularly, to a method for fabricating a spiral inductor used in a monolithic microwave integrated circuit on a silicon substrate using semiconductor fabrication processes. The method for fabricating an inductor, comprising the steps of: forming a first dielectric layer on a silicon substrate and forming a first metal wire on the first dielectric layer, wherein the first metal wire is in contact with an active element formed on the silicon substrate; and alternatively forming dielectric layers and metal layers, wherein the metal layers are electrically connected with an upper metal wire and a lower metal wire and wherein the metal layers are patterned using the dielectric layers as etching mask, whereby a metal corrosion is prevented by using the spiral dielectric pattern as the etching mask.
    Type: Grant
    Filed: October 7, 1998
    Date of Patent: May 28, 2002
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Min Park, Cheon Soo Kim, Hyun Kyu Yu
  • Publication number: 20020053699
    Abstract: An HF power device in an HF transistor includes a semiconductor layer as a first conductive type, a field area formed in a trench structure on one side of the semiconductor layer, gate electrode formed on a given surface of the semiconductor layer, a channel layer as a second conductive type laterally diffused from the field area to a width containing both sides of the gate electrode, and formed on the surface of the semiconductor layer, a source area as the second conductive type formed within the channel layer between one side of the gate electrode and the field area, a drain area as the second conductive type formed on the surface of the semiconductor layer with a given interval from another side of the gate electrode, a sinker as the first conductive type provided as a column shape of a trench structure for dividing into two source areas by a piercing through the source area, and connected to the semiconductor layer, an LDD area as the second conductive type formed on the surface of the semiconductor laye
    Type: Application
    Filed: December 28, 2000
    Publication date: May 9, 2002
    Inventors: Cheon-Soo Kim, Hyun-Kyu Yu, Nam Hwang, Jung-Woo Park