Abstract: A method for fabricating an inductor device includes the steps of forming a plurality of trenches in a substrate by selectively etching the substrate, implanting dopants into sidewalls and bottom portion of each trench, forming an oxide layer by oxidizing the trenches and the substrate and simultaneously forming a doped layer in the surroundings of the trenches by diffusing the dopants into the substrate, and forming a dielectric layer on a resultant structure to fill the entrance of the trenches, thereby forming air-gap layers inside the trenches, thereby reducing a parasitic capacitance and a magnetic coupling.

Abstract: A fabrication method of high performance integrated inductor devices using a substrate conversion technique is disclosed. By employing the trench-shaped porous silicon with high insulating property, the lossy characteristic of the silicon substrate is essentially to minimize. Also, by employing the conductive doped layer interposed between the porous silicon layer and the silicon substrate, the parasitic capacitance between metal lines and the silicon substrate is remarkably decreased. The present invention allows fabrication of high performance integrated inductors having high quality factor. Also, this invention prevents mutual-coupling between the silicon substrate and metal lines. As a result, integrated inductor devices according to this invention is readily adaptable for use in radio frequency integrated circuit (RF IC).

Abstract: The present invention relates to a on silicon substrate, specifically to an inductor device and manufacturing method thereof for enhancing the quality factor of the inductor by disposing trenches on a silicon substratre, and by filling the inside of the trenches with polycrystalline polysilicon not doped with impurities. The present invention provides an inductor device and a manufacturing method thereof which can improve the quality factor by increasing resistance of the substrate by forming deep trenches disposed in specific patterns on a low-resistance silicon substrate and filling polycrystalline silicon not doped with impurities, and by reducing parasitic capacitance between the inductor and the silicon substrate.

Abstract: An apparatus for improving linearity of small signal according to the present invention comprises a least of one non-linear signal generating means for receiving a first DC bias larger than a threshold voltage and for generating a non-linear signal; feedback means for returning the non-linear signal from said a least of one non-linear signal generating means; and amplifying means for receiving, amplifying and outputting to an output unit, a second DC bias larger than the threshold voltage and a reversed and feedback non-linear signal such that the non-linear signal is cancelled. The linearizers according to the present invention have a higher linearity and a simple constitution, and thereby being used for various terminals.

Abstract: Inductors used for impedance matching in the radio frequency integrated circuits is disclosed. In the integrated inductor device according to the present invention, an additional electrode is arranged in surroundings of an inductor metal line, and the reverse bias voltage is applied to the region between the substrate and the electrode so as to form a depletion layer. Therefore, the substrate biasing is effected and thus an inductor having improved performance can be formed by decreasing the parasitic capacitance between the inductor metal line and the substrate. The present invention can also be applied to another semiconductor device having metal lines and pads.

Abstract: A method for manufacturing a semiconductor device having a stacked gate electrode structure of self-aligned polysilicon-metal, which is capable of minimizing the variation in structural and electrical characteristics of the gate electrode, while utilizing the manufacturing process of forming a conventional silicone semiconductor memory device, is disclosed. According to the method for manufacturing a semiconductor device of the present invention, the conventional technique generally used in the manufacturing process of forming the silicon semiconductor device can be effectively utilized. Further, an excessive etch loss in the oxide layer can be restrained by using the oxide spacer of the self-aligned oxide layer in forming the metal layer at the gate electrode structure. Furthermore, it has an advantageous effect that the stable electrical characteristics of the resulting device can be obtained by using the polysilicon layer as a basic constituting material of the gate electrode thereof.

Abstract: An inductor device with a MOS transistor internally installed is disclosed, in which an inductor can be arbitrarily connected in series or in parallel to the respective terminals of MOS transistors by applying a multi-layer wiring technique, thereby reducing the chip area. Within an inductor structure, MOS transistors which have an active region width of W .mu.m are formed in the number of n, and an inductor wire is connected to an arbitrary terminal of the MOS transistors by employing a multi-layer metal wiring process. Thus the inductor is connected to an arbitrary terminal of the MOS transistors in series. Thus an inductor device in which MOS transistors having a channel width of W.times.n .mu.m are internally installed is formed.

Abstract: Methods for foming an inductor devices used for impedance matching in the radio frequency integrated circuits are disclosed. In the integrated inductor device according to the present invention, an additional electrode is arranged in surroundings of an inductor metal line, and the reverse bias voltage is applied to the region between the substrate and the electrode so as to form a depletion layer. Therefore, the substrate biasing is effected and thus an inductor having improved performance can be formed by decreasing the parasitic capacitance between the inductor metal line and the substrate. The present invention can also be applied to another semiconductor device having metal lines and pads.

Abstract: There are disclosed a semiconductor device having electrical elements buried a SOI substrate and a manufacturing method thereof, the manufacturing method of the invention comprising the steps of: (a) forming a first isolating insulator layer at a seed wafer by using an isolation mask, depositing a second isolating insulator layer overlying the first isolating insulator layer and the seed wafer, and defining contact holes by using a contact mask to form contacts on the seed wafer; (b) depositing a first polysilicon layer on the second isolating insulator layer and the contacts and doping an impurity into the first polysilicon layer; (c) patterning the first polysilicon layer to define an electrical element, depositing an insulating layer around the electrical element, and forming a second polysilicon layer overlying the second isolating insulator layer and the insulating layer; (d) doping an impurity into the second polysilicon layer for connecting with a handling wafer, and polishing the second polysilicon la