Abstract: A semiconductor process chamber is provided. The semiconductor process chamber includes a susceptor on which a plurality of wafers are disposed; a showerhead structure opposing the susceptor and disposed to be spaced apart from the susceptor; a plurality of plates opposing the susceptor and disposed to be spaced apart from the susceptor; and a blocking structure disposed between plates, among the plurality of plates, disposed adjacent to each other, wherein a distance between the showerhead structure and the susceptor is less than a distance between the plurality of plates and the susceptor, and a distance between the blocking structure and the susceptor is less than the distance between the plurality of plates and the susceptor.

Abstract: A semiconductor device includes a substrate, a tunnel insulation pattern on the substrate, a charge storage pattern on the tunnel insulation pattern, a dielectric pattern having a width smaller than a width of the charge storage pattern on the charge storage pattern, a control gate having a width greater than the width of the dielectric pattern on the dielectric pattern, and a metal-containing gate on the control gate.

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract: A semiconductor device includes a substrate, a tunnel insulation pattern on the substrate, a charge storage pattern on the tunnel insulation pattern, a dielectric pattern having a width smaller than a width of the charge storage pattern on the charge storage pattern, a control gate having a width greater than the width of the dielectric pattern on the dielectric pattern, and a metal-containing gate on the control gate.

Abstract: A semiconductor device includes a substrate, a tunnel insulation pattern on the substrate, a charge storage pattern on the tunnel insulation pattern, a dielectric pattern having a width smaller than a width of the charge storage pattern on the charge storage pattern, a control gate having a width greater than the width of the dielectric pattern on the dielectric pattern, and a metal-containing gate on the control gate.

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract: A non-volatile memory device having a vertical structure includes a semiconductor layer, a sidewall insulation layer extending in a vertical direction on the semiconductor layer, and having one or more protrusion regions, first control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of portions of the sidewall insulation layer where the one or more protrusion regions are not formed and second control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of the one or more protrusion regions.

Abstract: A semiconductor device includes a substrate, a tunnel insulation pattern on the substrate, a charge storage pattern on the tunnel insulation pattern, a dielectric pattern having a width smaller than a width of the charge storage pattern on the charge storage pattern, a control gate having a width greater than the width of the dielectric pattern on the dielectric pattern, and a metal-containing gate on the control gate.

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.