Abstract: A test apparatus for testing a multi-chip package comprising a multiplicity of semiconductor chips, which includes a test driver having one drive channel and at least one input/output channel. A test board is mounted with the multi-chip package. Drive pins of the semiconductor chips are parallel connected to the drive channel, and input/output pins of the semiconductor chips are parallel connected to the input/output channel.

Abstract: A semiconductor device test handler for maintaining stable temperature in a test environment may include a loading unit that loads a plurality of semiconductor devices mounted on a test tray; a soak chamber configured to receive the test tray from the loading unit and to age the semiconductor devices at an aging temperature; and a test chamber configured to receive and test the aged semiconductor devices. The test chamber may include: a test board; a first chamber; a second chamber; one or more pipelines connected to the first and second chambers that allow a temperature-control medium to flow between the first and second chambers; a de-soak chamber that further ages the tested semiconductor devices so that the tested semiconductor devices substantially return to ambient temperature; and a sorting and unloading unit that sorts the tested semiconductor devices according to results of the test and that unloads the sorted semiconductor devices.

Abstract: Embodiments of the invention connect a plurality of devices under test (DUTS) in a parallel manner and a high test current is selectively applied to each DUT. The apparatus to test a plurality of DUTs includes a plurality of power sources providing the test current to a plurality of DUTs; and switching devices connected to the respective DUTs and power sources and selectively providing the test current. In addition, the apparatus has at least one control unit to control the switching devices. Furthermore, a group of DUTs from the plurality of DUTs is connected between two of the plurality of power sources in a parallel manner, and the test current is selectively provided to one DUT from the group of DUTs according to the operation of the switching devices.

Abstract: A calibration method and a semiconductor testing apparatus, including N drivers, N being a natural number no less than two, at least one transmission path coupled to at least one of the N drivers, at least one calibration board coupled to the at least one transmission path, N comparators, and N delay paths, such that each delay path of the N delay paths has a skew value and is coupled between the calibration board and one of the N comparators.

Abstract: A test kit for a semiconductor package and a method of testing a semiconductor package using the same are provided. The test kit may include a pick-and-place tool for loading/unloading a semiconductor package, a head assembly for guiding a semiconductor package released from the pick-and-place tool, and a socket for receiving the semiconductor package from the pick-and-place tool. The method may include performing pre-alignment by inserting one or more slide posts of an alignment tool into a socket, releasing a semiconductor package through a package guider, and attaching the semiconductor package onto a socket.

Abstract: A forced air heat exhaust type of burn-in test apparatus for packages: A first air supply duct provides air to the burn-in chamber and a second air supply duct provides air to supply tubes that direst air into the test sockets that hold the packages. The test sockets have a structure that allows air ventilation of the conductive balls. Accordingly, the apparatus can control the temperature around the packages as well as the temperature in the burn-in chamber, thus preventing conductive ball-melting.

Abstract: In one embodiment, a connector is made using a mixture of insulating silicone powder and conductive powder. The connector comprises a connector body formed from the insulating silicone powder and on or more preferably regularly arrayed conductive silicone members that are formed by migrating the conductive powder to a site of the connector corresponding to a solder ball of the semiconductor package. The conductive silicone member comprises a high-density conductive silicone part formed to be proximate an upper surface of the connector body and to protrude therefrom and a low-density conductive silicone part formed in substantial vertical alignment beneath the high-density conductive silicone part, the low-density conductive silicone part having a lower surface exposed from a lower surface of the connector body.

Abstract: A test board for a semiconductor device tester having a modified input/output printed circuit pattern and a testing method using the same are provided. In an embodiment, a modified input/output printed circuit pattern is formed and controlled by a test program, wherein the modified input/output printed circuit pattern is divided into a drive terminal and a comparator terminal, one of the terminals being connected to one input pin of a device under test (DUT) and the other being connected to an output pin of the DUT, unlike a typical input/output printed circuit pattern of the test board that is formed to be connected to one output pin of a DUT. Thus, it is possible to increase the number of devices under parallel test and to test semiconductor memory devices having larger capacity by using limited resources of the tester.

Abstract: The present invention provides a contact-free test system for testing a semiconductor device. The contact-free test system comprises a test signal member applying a test signal to the semiconductor device, an electronic beam radiator generating a first electronic beam and radiating it to an area of the semiconductor device, a detector to detect a second electronic beam reflected from the semiconductor device, and a comparator to compare the test signal with the second electronic beam.

Abstract: A test kit for a semiconductor package and a method for testing the semiconductor package using the same are provided. The test kit for a semiconductor package includes a pick-and-place tool for picking up and loading/unloading the semiconductor package, a head assembly having a package guider and a socket guider, and a socket which is positioned under the head assembly. The socket guider performs a pre-alignment function for a correct operation of the package guider, before the package guider starts operating. The package guider aligns the semiconductor package.

Abstract: A test apparatus for testing a multi-chip package comprising a multiplicity of semiconductor chips, which includes a test driver having one drive channel and at least one input/output channel. A test board is mounted with the multi-chip package. Drive pins of the semiconductor chips are parallel connected to the drive channel, and input/output pins of the semiconductor chips are parallel connected to the input/output channel.

Abstract: A test apparatus for testing a multi-chip package comprising a multiplicity of semiconductor chips, which includes a test driver having one drive channel and at least one input/output channel. A test board is mounted with the multi-chip package. Drive pins of the semiconductor chips are parallel connected to the drive channel, and input/output pins of the semiconductor chips are parallel connected to the input/output channel.

Abstract: A forced air heat exhaust type of burn-in test apparatus for packages: A first air supply duct provides air to the burn-in chamber and a second air supply duct provides air to supply tubes that direst air into the test sockets that hold the packages. The test sockets have a structure that allows air ventilation of the conductive balls. Accordingly, the apparatus can control the temperature around the packages as well as the temperature in the burn-in chamber, thus preventing conductive ball-melting.

Abstract: Embodiments of the invention connect a plurality of devices under test (DUTS) in a parallel manner and a high test current is selectively applied to each DUT. The apparatus to test a plurality of DUTs includes a plurality of power sources providing the test current to a plurality of DUTs; and switching devices connected to the respective DUTs and power sources and selectively providing the test current. In addition, the apparatus has at least one control unit to control the switching devices. Furthermore, a group of DUTs from the plurality of DUTs is connected between two of the plurality of power sources in a parallel manner, and the test current is selectively provided to one DUT from the group of DUTs according to the operation of the switching devices.

Abstract: A test apparatus for testing a multi-chip package comprising a multiplicity of semiconductor chips, which includes a test driver having one drive channel and at least one input/output channel. A test board is mounted with the multi-chip package. Drive pins of the semiconductor chips are parallel connected to the drive channel, and input/output pins of the semiconductor chips are parallel connected to the input/output channel.

Abstract: A test kit for a semiconductor package and a method for testing the semiconductor package using the same are provided. The test kit for a semiconductor package includes a pick-and-place tool for picking up and loading/unloading the semiconductor package, a head assembly having a package guider and a socket guider, and a socket which is positioned under the head assembly. The socket guider performs a pre-alignment function for a correct operation of the package guider, before the package guider starts operating. The package guider aligns the semiconductor package.

Abstract: A testing system for memory Devices Under Test (DUTs) uses an improved wiring scheme to increase the parallel test number. In a preferred embodiment, the parallel testing system increases the parallel test number by commonly connecting data input/output pins of the memory devices to an input/output channel of the testing system. Driving channels may also be connected in parallel to driving pins of the plurality of semiconductor memory devices under test.

Abstract: When high speed memory devices are tested using a tester having a lower operating frequency than the operational speed of the memory device, limit conditions for the tester signals are required to prevent the interference between the tester and device signals. The present invention provides the limit conditions for the shift and strobe signal. The strobe signal is delivered to comparators with a delivery delay time defining the dead time zone. The shift signal controls the data path of the device to and from a driver and a comparator. When the strobe signal is within the present test cycle, the shift signal of a read cycle must be activated at the same time or earlier than the activation time of the WE/ signal of the next write cycle and the shift signal of a write cycle must start at the same time or earlier than the activation time of the OE/ signal of the next read cycle. When the strobe signal is outside of the test cycle, the shift signal must meet prescribed maximum and minimum timing conditions.

Abstract: A test method can test high speed synchronous memory devices by using a tester having a minimum rate and a minimum clock cycle slower than operating speed of the devices to be tested. The test method transforms a pulse signal generated by the tester to be transformed into a clock signal having a frequency higher than the minimum rate, a test cycle of the test equipment then being determined based on a cycle time of the pulse signal, the operating cycle of the IC devices being determined based on a cycle time of the clock signal, and an input setup time and an input hold time of control signals which are supplied from the tester to the devices are separately measured for every two or more operating cycles of the IC devices.