Abstract: In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability.

Abstract: A semiconductor package may have a semiconductor chip that includes a chip pad formed on a substrate including an integrated circuit, and a passivation layer exposing the chip pad, a first redistribution wiring layer that is connected to the chip pad and extends on the semiconductor chip and includes a wire bonding pad to provide wire bonding and a first solder pad to connect the first redistribution wiring layer to a second semiconductor chip, and a second redistribution wiring layer that is connected to the first redistribution wiring layer on the first redistribution wiring layer and includes a second solder pad to connect the second redistribution wiring layer to a third semiconductor chip.

Abstract: Provided are semiconductor packages and methods of manufacturing the semiconductor package. The semiconductor packages may include a substrate including a chip pad, a redistributed line which is electrically connected to the chip pad and includes an opening. The semiconductor packages may also include an external terminal connection portion, and an external terminal connection pad which is disposed at an opening and electrically connected to the redistributed line. The present general inventive concept can solve the problem where an ingredient of gold included in a redistributed line may be prevented from being diffused into an adjacent bump pad to form a void or an undesired intermetallic compound. In a chip on chip structure, a plurality of bumps of a lower chip are connected to an upper chip to improve reliability, diversity and functionality of the chip on chip structure.

Abstract: In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability.

Abstract: The invention provides a semiconductor device. The semiconductor device includes a semiconductor chip having an active surface on which pads are disposed, a passivation layer pattern disposed to cover the active surface of the semiconductor chip and to expose the pads, a first insulation layer pattern disposed on the passivation layer pattern, a second insulation layer pattern disposed on only a portion of the first insulation layer pattern, and redistribution line patterns electrically connected to the pads and disposed so as to extend across the second insulation layer pattern and the first insulation layer pattern. A method of fabricating the same is also provided.

Abstract: In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability.

Abstract: A wafer level semiconductor module may include a module board and an IC chip set mounted on the module board. The IC chip set may include a plurality of IC chips having scribe lines areas between the adjacent IC chips. Each IC chip may have a semiconductor substrate having an active surface with a plurality of chip pads and a back surface. A passivation layer may be provided on the active surface of the semiconductor substrate of each IC chip and may having openings through which the chip pads may be exposed. Sealing portions may be formed in scribe line areas.

Abstract: A semiconductor module can include a printed circuit board (PCB) and a semiconductor package inserted into an inner space of the PCB. The semiconductor package may be electrically connected to the PCB. The PCB may thus surround the semiconductor package so that cracks may not be generated in the outer terminals.

Abstract: Provided are methods of fabricating semiconductor chips, semiconductor chips formed by the methods, and chip-stack packages having the semiconductor chips. One embodiment specifies a method that includes patterning a scribe line region of a semiconductor substrate to form a semiconductor strut spaced apart from edges of a chip region of the semiconductor substrate.

Abstract: A semiconductor package with improved joint reliability and a method of fabricating the semiconductor package are disclosed. A conductive connector may be formed on a surface of a semiconductor wafer on which semiconductor devices may be arranged. A first insulating layer including a first opening through which a portion of the connection pad is exposed may be formed on the connection pad and the semiconductor wafer. A rewiring line electrically connected to an exposed portion of the connection pad may be formed on the first insulating layer. A second insulating layer including a second opening through which a portion of the rewiring line is exposed may be formed on the rewiring line and the first insulating layer. A connection terminal including one or more entangled wires may be formed on an exposed portion of the rewiring line so as to be electrically connected to the rewiring line.

Abstract: A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal layer pattern is formed over the first metal layer pattern and within the via hole. A plug is formed within the via hole. Thereafter, a passivation layer is formed to overlie the final metal layer pattern.

Abstract: A chip stack package is provided, wherein semiconductor chips having different die sizes are stacked by arranging pads in a scribe region through a redistribution process, so that the thickness of the package can be reduced. A method of fabricating the chip stack package is also provided. In the chip stack package, a plurality of circuit patterns are arranged on one surface of a substrate, and a unit semiconductor chip is mounted thereon. The unit semiconductor chip includes a plurality of semiconductor chips sequentially stacked on the substrate. The semiconductor chips of the unit semiconductor chip have different die sizes. One of the semiconductor chips includes a plurality of first pads arranged in a first chip region, and the other semiconductor chips include second pads arranged in a scribe region at an outside of a second chip region defined by the scribe region.

Abstract: Semiconductor devices and methods of forming the same, including forming a chip pad on a chip substrate, forming a passivation layer on the chip pad and the chip substrate, forming a first insulation layer on the passivation layer, forming a recess and a first opening in the first insulation layer, forming a second opening in the passivation layer to correspond to the first opening, forming a redistribution line in a redistribution line area of the recess, the first opening, and the second opening, forming a second insulation layer on the redistribution line and the first insulation layer, and forming an opening in the second insulation to expose a portion of the redistribution line as a redistribution pad.

Abstract: A ball grid array type board on chip package may include an integrated circuit chip having an active surface that supports a plurality of contact pads. An interposer may be adhered to the active surface of the integrated circuit chip. At least one hole may be provided through the interposer to expose the contact pads. A board, which may have a first surface supporting a plurality of metal lines, may have a second surface adhered to the interposer. The board may have an opening through which the contact pads may be exposed. A plurality of bonding wires may connect the contact pads to the metal lines through the opening.

Abstract: A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal layer pattern is formed over the first metal layer pattern and within the via hole. A plug is formed within the via hole. Thereafter, a passivation layer is formed to overlie the final metal layer pattern.

Abstract: In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability.

Abstract: Provided is a method of fabricating a chip-on-chip (COC) semiconductor device. The method of fabricating a chip-on-chip (COC) semiconductor device may include preparing a first semiconductor device with a metal wiring having at least one discontinuous spot formed therein, preparing a second semiconductor device with at least one bump formed on a surface of the second semiconductor device corresponding to the at least one discontinuous spot, aligning the first semiconductor device onto the second semiconductor device, and connecting the at least one bump of the second semiconductor device to the at least one discontinuous spot formed in the metal wiring of the first semiconductor device.

Abstract: Wafer level packages and methods of fabricating the same are provided. In one embodiment, one of the methods comprises forming semiconductor chips having a connection pad on a wafer, patterning a bottom surface of the wafer to form a trench under the connection pad, patterning a bottom surface of the trench to form a via hole exposing the bottom surface of the connection pad, and forming a connecting device connected to the connection pad through the via hole. The invention provides a wafer level package having reduced thickness, lower fabrication costs, and increased reliability compared to conventional packages.

Abstract: In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability.

Abstract: Provided are a wafer level chip scale package in which a redistribution process is applied at a wafer level, a manufacturing method thereof, and a semiconductor chip module including the wafer level chip scale package. The wafer level chip scale package includes a semiconductor chip having a bonding pad, a first insulating layer disposed on the semiconductor chip so as to expose the bonding pad, a redistribution line disposed on the exposed bonding pad and the first insulating layer, a sacrificial layer disposed below a redistribution pad of the redistribution line, a second insulating layer disposed on the redistribution line so as to expose the redistribution pad and including a crack inducement hole disposed beside the sacrificial layer, and an external connection terminal attached to the redistribution pad.