Patents by Inventor Hyun-Suk Lee

Hyun-Suk Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12255065
    Abstract: A method of manufacturing a semiconductor device includes: forming electrode holes by etching a mold structure including a mold layer and a support layer which are stacked on a substrate; forming lower electrode pillars filling the electrode holes; etching a portion of the support layer between the lower electrode pillars to form a support pattern having a through-hole exposing a portion of a top surface of the mold layer; removing the mold layer through the through-hole to expose sidewalls of the lower electrode pillars; and selectively forming lower electrode patterns on the sidewalls and top surfaces of the lower electrode pillars.
    Type: Grant
    Filed: December 5, 2023
    Date of Patent: March 18, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Suk Lee, Jungoo Kang, Gihee Cho, Sanghyuck Ahn
  • Patent number: 12243479
    Abstract: A pixel circuit and a display panel including the same are disclosed according to embodiments. The pixel circuit according to embodiments includes a first pixel circuit including a first EM transistor to which a pulse of a first EM signal is applied, and a first driving transistor for driving a first light emitting element; and a second pixel circuit including a second EM transistor to which a pulse of a second EM signal is applied, and a second driving transistor for driving a second light emitting element. A node between the first EM transistor and the first driving transistor and a node between the second EM transistor and the second driving transistor are connected.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: March 4, 2025
    Assignee: LG Display Co., Ltd.
    Inventors: Jin Woo Jung, Sang Jin Nam, Hyun Suk Lee, Seung Jin Yoo
  • Patent number: 12205952
    Abstract: A semiconductor device includes; a bottom electrode on a substrate, a supporting pattern between the bottom electrode and an adjacent bottom electrode, a top electrode covering the bottom electrode and the supporting pattern, and a dielectric layer between the bottom electrode and the top electrode and between the supporting pattern and the top electrode. The bottom electrode may include a first portion including a seam and a second portion on the first portion, a top end of the second portion may be disposed at a height lower than an upper surface of the supporting pattern, and a portion of a bottom end of the second portion may be exposed to the seam.
    Type: Grant
    Filed: December 13, 2023
    Date of Patent: January 21, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gihee Cho, Sanghyuck Ahn, Hyun-Suk Lee, Jungoo Kang, Jin-Su Lee, Hongsik Chae
  • Patent number: 12154516
    Abstract: The present disclosure relates to a display panel and a display device using the same. The display panel includes a pixel array in which a plurality of data lines, a plurality of gate lines crossing the data lines, and a plurality of pixels are disposed; a first gate driver configured to supply a gate signal to gate lines connected to pixels disposed in a first area of the pixel array; and a second gate driver configured to receive a carry signal from the first gate driver and supply a gate signal to gate lines connected to pixels disposed in a second area of the pixel array. The second gate driver includes a signal transmission unit disposed in the pixel array to receive the carry signal from the first gate driver.
    Type: Grant
    Filed: July 7, 2023
    Date of Patent: November 26, 2024
    Assignee: LG Display Co., Ltd.
    Inventors: Hyun Suk Lee, Seung Taek Oh
  • Patent number: 12119374
    Abstract: A semiconductor device and a method of manufacturing the same, the device including a plurality of lower electrodes on a semiconductor substrate; a support pattern connecting the lower electrodes at sides of the lower electrodes; and a dielectric layer covering the lower electrodes and the support pattern, wherein each of the plurality of lower electrodes includes a pillar portion extending in a vertical direction perpendicular to a top surface of the semiconductor substrate; and a protrusion protruding from a sidewall of the pillar portion so as to be in contact with the support pattern, the pillar portion includes a conductive material, the protrusion includes a same conductive material as the pillar portion and is further doped with impurities.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: October 15, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gihee Cho, Sangyeol Kang, Jungoo Kang, Taekyun Kim, Jiwoon Park, Sanghyuck Ahn, Jin-Su Lee, Hyun-Suk Lee, Hongsik Chae
  • Publication number: 20240234485
    Abstract: An integrated circuit device includes a conductive region on a substrate and a lower electrode structure including a main electrode part spaced apart from the conductive region and a bridge electrode part between the main electrode part and the conductive region. A dielectric layer contacts an outer sidewall of the main electrode part. To manufacture the integrated circuit device, a preliminary bridge electrode layer is formed in a hole of a mold pattern on the substrate, and the main electrode part is formed on the preliminary bridge electrode layer in the hole. The mold pattern is removed to expose a sidewall of the preliminary bridge electrode layer, and a portion of the preliminary electrode part is removed to form the bridge electrode part. The dielectric layer is formed to contact the outer sidewall of the main electrode part.
    Type: Application
    Filed: March 25, 2024
    Publication date: July 11, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jun-goo KANG, Hyun-suk LEE, Gi-hee CHO
  • Publication number: 20240220551
    Abstract: The present disclosure relates to an electronic apparatus executing auto-crawling based on artificial intelligence, including: a crawling unit acquiring images including a target using an artificial intelligence model; a target identifying unit identifying a target matching the acquired image; and a processor controlling operations of the crawling unit and the target identifying unit. The processor classifies and searches for images including the target, among images stored in a predetermined area, according to crawling levels, and performs vision processing of the automatically searched images including the target to identify the target, and transmits the target and information on the target to a server or stores the target and information on the target in a memory.
    Type: Application
    Filed: September 11, 2023
    Publication date: July 4, 2024
    Applicant: doinglab Corp.
    Inventors: Song Baik JIN, Hyun Suk LEE, Chae Yoon HAN
  • Patent number: 12009387
    Abstract: An integrated circuit device includes a conductive region on a substrate and a lower electrode structure including a main electrode part spaced apart from the conductive region and a bridge electrode part between the main electrode part and the conductive region. A dielectric layer contacts an outer sidewall of the main electrode part. To manufacture the integrated circuit device, a preliminary bridge electrode layer is formed in a hole of a mold pattern on the substrate, and the main electrode part is formed on the preliminary bridge electrode layer in the hole. The mold pattern is removed to expose a sidewall of the preliminary bridge electrode layer, and a portion of the preliminary electrode part is removed to form the bridge electrode part. The dielectric layer is formed to contact the outer sidewall of the main electrode part.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: June 11, 2024
    Assignee: Samsung Electronics, Co. Ltd.
    Inventors: Jun-goo Kang, Hyun-suk Lee, Gi-hee Cho
  • Patent number: 11978765
    Abstract: An integrated circuit device includes a conductive region on a substrate and a lower electrode structure including a main electrode part spaced apart from the conductive region and a bridge electrode part between the main electrode part and the conductive region. A dielectric layer contacts an outer sidewall of the main electrode part. To manufacture the integrated circuit device, a preliminary bridge electrode layer is formed in a hole of a mold pattern on the substrate, and the main electrode part is formed on the preliminary bridge electrode layer in the hole. The mold pattern is removed to expose a sidewall of the preliminary bridge electrode layer, and a portion of the preliminary electrode part is removed to form the bridge electrode part. The dielectric layer is formed to contact the outer sidewall of the main electrode part.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: May 7, 2024
    Assignee: Samsung Electronics, Co. Ltd.
    Inventors: Jun-goo Kang, Hyun-suk Lee, Gi-hee Cho
  • Publication number: 20240120196
    Abstract: A method of manufacturing a semiconductor device includes: forming electrode holes by etching a mold structure including a mold layer and a support layer which are stacked on a substrate; forming lower electrode pillars filling the electrode holes; etching a portion of the support layer between the lower electrode pillars to form a support pattern having a through-hole exposing a portion of a top surface of the mold layer; removing the mold layer through the through-hole to expose sidewalls of the lower electrode pillars; and selectively forming lower electrode patterns on the sidewalls and top surfaces of the lower electrode pillars.
    Type: Application
    Filed: December 5, 2023
    Publication date: April 11, 2024
    Inventors: Hyun-Suk Lee, Jungoo Kang, Gihee Cho, Sanghyuck Ahn
  • Publication number: 20240113122
    Abstract: A semiconductor device includes; a bottom electrode on a substrate, a supporting pattern between the bottom electrode and an adjacent bottom electrode, a top electrode covering the bottom electrode and the supporting pattern, and a dielectric layer between the bottom electrode and the top electrode and between the supporting pattern and the top electrode. The bottom electrode may include a first portion including a seam and a second portion on the first portion, a top end of the second portion may be disposed at a height lower than an upper surface of the supporting pattern, and a portion of a bottom end of the second portion may be exposed to the seam.
    Type: Application
    Filed: December 13, 2023
    Publication date: April 4, 2024
    Inventors: Gihee Cho, Sanghyuck Ahn, Hyun-Suk Lee, Jungoo Kang, Jin-Su Lee, Hongsik Chae
  • Patent number: 11881482
    Abstract: A semiconductor device includes; a bottom electrode on a substrate, a supporting pattern between the bottom electrode and an adjacent bottom electrode, a top electrode covering the bottom electrode and the supporting pattern, and a dielectric layer between the bottom electrode and the top electrode and between the supporting pattern and the top electrode. The bottom electrode may include a first portion including a seam and a second portion on the first portion, a top end of the second portion may be disposed at a height lower than an upper surface of the supporting pattern, and a portion of a bottom end of the second portion may be exposed to the seam.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: January 23, 2024
    Inventors: Gihee Cho, Sanghyuck Ahn, Hyun-Suk Lee, Jungoo Kang, Jin-Su Lee, Hongsik Chae
  • Patent number: 11875992
    Abstract: Semiconductor devices are provided. A semiconductor device includes a first portion of a lower electrode structure on a substrate. The semiconductor device includes a first support pattern being in contact with a first portion of a sidewall of the first portion of the lower electrode structure. The semiconductor device includes a second portion of the lower electrode structure on a second portion of the sidewall of the first portion of the lower electrode structure. The semiconductor device includes an upper electrode on the second portion of the lower electrode structure and on the first support pattern. Moreover, the semiconductor device includes a dielectric layer between the upper electrode and the second portion of the lower electrode structure.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: January 16, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Suk Lee, Jungoo Kang, Gihee Cho, Sanghyuck Ahn
  • Publication number: 20240014252
    Abstract: A semiconductor device includes a substrate, first and second supporter patterns spaced vertically from the substrate, the second supporter pattern being spaced vertically from the first supporter pattern, a lower electrode hole extending vertically on the substrate, a lower electrode inside the lower electrode hole, contacting a sidewall of the first and second supporter patterns, the lower electrode including a first layer along a portion of a sidewall and bottom surface of the lower electrode hole, a second layer between the first layers, and a third layer on an upper surface of the first and second layers, the first and second layers including a material different from the second layer, and a sidewall of at least a portion of the third layer being concave toward the third layer, overlapping the second layer in the vertical direction, and being spaced apart from the second layer in the vertical direction.
    Type: Application
    Filed: March 10, 2023
    Publication date: January 11, 2024
    Inventors: Hong Sik CHAE, Tae Kyun KIM, Ji Hoon AN, Hyun-Suk LEE, Gi Hee CHO, Jae Hyoung CHOI
  • Patent number: 11861268
    Abstract: A method for auto-generating an AutoCAD drawing includes providing an interface for extracting only input data required for drawing equipment from strength calculation data, displaying all components and nozzles constituting the equipment and providing or correcting information thereon. The AutoCAD drawing is automatically generated based on information on all components constituting the equipment and nozzles.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: January 2, 2024
    Assignees: SAMSUNG ENGINEERING CO., LTD.
    Inventors: Gyun Ho Ha, Hyun Suk Lee, Young Sik Ji, Yun Ha Shin, Geun Yong Choi, Do Young Park, Sung Jin Moon, Won Seok Choi, Ji Yoon Hyun, Byueong Kook Cheo, Dae Seong Kim
  • Patent number: 11830603
    Abstract: Disclosed are a system and a method for providing nutritional information based on image analysis using artificial intelligence. The system includes: at least one imaging device acquiring at least one image including at least one dish or at least one food contained in each dish; a service providing apparatus for detecting at least one food included in the at least one image when the at least one image is received, confirming the name of each detected food on the basis of a learning model, mapping food information included in pre-stored food information on the basis of the confirmed name, and generating nutritional information using the mapped food information; and a user terminal for visualizing and displaying the nutritional information when the nutritional information is received.
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: November 28, 2023
    Assignee: doinglab Corp.
    Inventors: Hyun Suk Lee, Song Baik Jin, Jae Yeol Kim, Dae Han Kim, Yoo Bin Shin, Chae Yoon Han
  • Patent number: 11812601
    Abstract: A semiconductor device includes a substrate, first and second supporter patterns stacked sequentially on the substrate in a first direction and spaced apart from an upper surface of the substrate, a lower electrode hole that extends through the first and second supporter patterns on the substrate in the first direction, an interface film on side walls and a bottom surface of the lower electrode hole, a lower electrode inside of the lower electrode hole on the interface film, a capacitor dielectric film that is in physical contact with side walls of the interface film, an uppermost surface of the interface film, and an uppermost surface of the lower electrode, the uppermost surface of the interface film is formed on a same plane as an upper surface of the second supporter pattern.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: November 7, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun Goo Kang, Sang Hyuck Ahn, Sang Yeol Kang, Jin-Su Lee, Hyun-Suk Lee, Gi Hee Cho, Hong Sik Chae
  • Publication number: 20230351973
    Abstract: The present disclosure relates to a display panel and a display device using the same. The display panel includes a pixel array in which a plurality of data lines, a plurality of gate lines crossing the data lines, and a plurality of pixels are disposed; a first gate driver configured to supply a gate signal to gate lines connected to pixels disposed in a first area of the pixel array; and a second gate driver configured to receive a carry signal from the first gate driver and supply a gate signal to gate lines connected to pixels disposed in a second area of the pixel array. The second gate driver includes a signal transmission unit disposed in the pixel array to receive the carry signal from the first gate driver.
    Type: Application
    Filed: July 7, 2023
    Publication date: November 2, 2023
    Applicant: LG DISPLAY CO., LTD.
    Inventors: Hyun Suk LEE, Seung Taek OH
  • Patent number: 11741910
    Abstract: The present disclosure relates to a display panel and a display device using the same. The display panel includes a pixel array in which a plurality of data lines, a plurality of gate lines crossing the data lines, and a plurality of pixels are disposed; a first gate driver configured to supply a gate signal to gate lines connected to pixels disposed in a first area of the pixel array; and a second gate driver configured to receive a carry signal from the first gate driver and supply a gate signal to gate lines connected to pixels disposed in a second area of the pixel array. The second gate driver includes a signal transmission unit disposed in the pixel array to receive the carry signal from the first gate driver.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: August 29, 2023
    Assignee: LG Display Co., Ltd.
    Inventors: Hyun Suk Lee, Seung Taek Oh
  • Patent number: 11704516
    Abstract: Disclosed is computing technology for managing information display of an electronic label which is connected to a management server via a network and displays electronic information. A moving device transmits images, which are obtained by photographing an electronic label and a product while being moved in a store, to a management server. The management server analyzes the images to extract information and detects changes in displayed products to register changed information. The management server performs inventory management using the extracted information. Further, the management server uses the extracted information to inform a store manager so that a location of a displayed product deviated from a place thereof is corrected.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: July 18, 2023
    Assignee: SOLUM CO., LTD.
    Inventors: Bo Il Seo, Hyun Suk Lee