Abstract: The present invention relates to a wearable pressure ulcer detection sensor, and the wearable pressure ulcer detection sensor according to the present invention includes a pressure sensor measuring pressure based on a change in capacitance caused by physical force, a temperature sensor measuring temperature based on a change in electrical conductivity due to electron hopping, and an impedance sensor including two electrodes spaced apart from each other and in contact with skin.

Abstract: An electrode insulating coating composition according to the present invention includes boehmite particles, a dispersant, a binder, and a solvent, wherein the dispersant includes two or more fatty acid compounds, and is included in an amount of 1.2 to 8.8 parts by weight with respect to 100 parts by weight of the boehmite particles.

Abstract: The present invention relates to an antigen-binding molecule comprising a heavy chain variable region comprising a heavy-chain complementarity-determining region 1 (HCDR1) comprising an amino acid sequence represented by Sequence No. 1, an HCDR2 comprising an amino acid sequence represented by Sequence No. 2, and an HCDR3 comprising an amino acid sequence represented by Sequence No. 3; a light-chain variable region comprising a light-chain complementarity-determining region 1 (LCDR1) comprising an amino acid sequence represented by Sequence No. 4, an LCDR2 comprising an amino acid sequence represented by Sequence No. 5, and an LCDR3 comprising an amino acid sequence represented by Sequence No. 6; wherein the antigen-binding molecule is a T cell receptor (TCR); and to a cell line expressing the same.

Abstract: Described systems, apparatuses, and methods relate to volatile memories that are refreshed to maintain data integrity, such as dynamic random-access memory (DRAM) and synchronous DRAM (SDRAM). A memory device includes multiple dies, with each die having a memory array to be refreshed. The multiple dies may be interconnected via at least one inter-die bus of the memory device. A memory controller sends a command to the memory device to enter a self-refresh mode. In response, a die of the multiple dies can enter the self-refresh mode and initiate or otherwise coordinate refresh operations of the other dies. To do so, the die may transmit at least one refresh-related command to at least one other die using the inter-die bus. Multiple different signaling schemes and timing approaches are disclosed. The described inter-die refresh control principles may be implemented in energy-efficient applications, such as in low-power double data rate (LPDDR) SDRAM.

Abstract: An electronic device includes a display layer in which an active region and a peripheral region proximate to the active region are defined and a controller that is configured to control the display layer. The display layer includes a plurality of pixels, a plurality of antenna patterns that transmit and receive a first signal having a predetermined frequency, and a switch connected to at least one of the plurality of antenna patterns. The controller provides, to the switch, a control signal to control the switch. The switch includes a first line to which a ground voltage is provided, a second line that is floated, a third line to which the first signal is provided, and a fourth line connected to the at least one of the plurality of antenna patterns and electrically connected to the first line, the second line, or the third line based on the control signal.

Abstract: An optical inspection apparatus includes a stage that supports a target substrate, the target substrate including a plurality of light emitting elements, a jig that applies an electrical signal to the target substrate, the jig including a regulation resistor, a microscope that generates magnified image data of the target substrate, a camera that captures the magnified image data to generate a color image of the target substrate, and an optical measurement unit that captures the magnified image data of the target substrate to generate a spectrum image and measure optical characteristics of the target substrate.

Abstract: The button structure including a front panel configured to define a body and having a mounting hole formed in a front surface of the front panel directed toward an interior of an occupant compartment, a button unit accommodated in the mounting hole and configured to selectively control various types of AV systems of a vehicle, a detection unit accommodated in the front panel and configured to detect a user's hand, a switch unit configured to operate various types of AV systems of the vehicle under the control of the button unit, and a lighting unit accommodated in a housing and configured to emit light to the button unit in response to a detection signal of the detection unit, in which the detection unit is disposed rearward of the button unit and positioned from the button unit in a direction opposite to the direction toward the interior of the occupant compartment.

Abstract: A circuit board according to an embodiment includes an insulating layer; and a via formed in the insulating layer; wherein a width of an upper surface of the via is greater than a width of a lower surface of the via, and wherein the width of the lower surface of the via is 75% to 95% of the width of the upper surface of the via.

Abstract: A lithium secondary battery includes a cathode formed from a cathode active material including a first cathode active material particle and a second cathode active material particle, an anode and a separator interposed between the cathode and the anode. The first cathode active material particle includes a lithium metal oxide including a continuous concentration gradient in at least one region between a central portion and a surface portion. The second cathode active material particle includes a lithium metal oxide including elements the same as those of the first cathode active material particle, and the second cathode active material particle has a uniform composition from a central portion to a surface.

Abstract: The present disclosure relates to an organic film polishing composition in which a high polishing speed is maintained not only for polymers, an SOC, and an SOH, but also for organic films strongly bonded by covalent bonds such as an amorphous carbon layer (ACL) or a diamond-like carbon (DLC) by including a polishing accelerator containing both a hydrophilic group and a hydrophobic group, and a polishing method using the same.

Abstract: A graft copolymer, and a graft copolymer composition having excellent particulate dispersibility in a curable resin such as an epoxy resin and is applicable as a particulate impact reinforcing agent, a curable resin composition including same, and methods of preparing them.

Abstract: A method for configuring an observable object as a digital twin in a digital twin system of any one domain is provided. The method for configuring a digital twin includes defining a purpose for expressing the observable as a digital twin in the domain, organizing data based on a role of the observable object in the domain, configuring the observable object into the digital twin based on the data for the purpose, and synchronizing the observable object and the digital twin.

Abstract: Systems, apparatuses, and methods related to a memory device and an associated host device are described. The memory device and the host device can include control logic that allow the memory device and host device to share refresh-timing information, which may allow either the memory device or the host, or both, to manage operations during time that is dedicated to, but unused for, refresh or self-refresh operations. Refresh-timing information shared from the host device may indicate elapsed time since the host device issued a refresh command to the memory device and/or how much time remains before the host device is scheduled to issue another refresh command. Refresh-timing information shared from the memory device may indicate elapsed time since the memory device performed a self-refresh operation and/or how much time remains before the memory device is scheduled to initiate or undergo another self-refresh operation.

Abstract: Described apparatuses and methods facilitate bus training with multiple dice, such as multiple memory dice. A controller can communicate with multiple dice to perform bus training by sending a test pattern and receiving in return a feedback pattern indicative of the bits detected by the dice. Because suitable signal timing can differ between dice, even those using the same bus, a controller may train each die separately from the others. In some situations, however, individualized training may be infeasible. To accommodate such situations, logic associated with two or more dice can combine, using at least one logical operation, bits as detected from the test pattern into a combined feedback pattern. A timing parameter that is jointly suitable for multiple dice can be determined, and the bus training may be concluded, responsive to the combined feedback pattern matching the test pattern. The multiple dice may be stacked or linked.

Abstract: Described apparatuses and methods relate to adaptive memory registers for a memory system that may support a nondeterministic protocol. To help manage power-delivery networks in a memory system, a device includes logic that can write values to memory registers associated with memory blocks of a memory array. The values indicate whether an associated memory block has been refreshed within a refresh interval. Other logic can read the registers to determine whether a block has been refreshed. The device also includes logic that can access data indicating a row address that was most recently, or is next to be, refreshed and write values representing the address to another register. The register can be read by other logic to determine whether a wordline potentially affected by an activation-based disturb event is near to being refreshed. These techniques can reduce the number of refresh operations performed, saving power and reducing costs.

Abstract: The present disclosure relates to a simulation apparatus for secondary battery production.

Abstract: Apparatuses and techniques for implementing an asymmetric read-write sequence for interconnected dies are described. The asymmetric read-write sequence refers to an asymmetric die-access sequence for read versus write operations. The “asymmetric” term refers to a difference in an order in which data is written to or read from interface and linked dies of the interconnected die architecture. The orders for the read and write operations can be chosen such that a delay associated with transferring data between the interconnected dies occurs as data passes between the interface die and a memory controller. With asymmetric read-write burst sequences, overall timing of the read and write operations of a memory device may be impacted less, if at all, by a timing delay associated with the interconnected die architecture.

Abstract: Described apparatuses and methods facilitate bus training with multiple dice, such as multiple memory dice. A controller can communicate with multiple dice over a bus to perform bus training by sending a test pattern and receiving in return a feedback pattern indicative of the bits detected by the dice. Because suitable signal timing can differ between dice, even those using the same bus, the controller may attempt to train each die separately from the others. In some situations, however, individualized training may be infeasible. To accommodate such situations, logic associated with two or more dice can combine the bits as detected from the test pattern into a combined feedback pattern. A timing parameter that is jointly suitable for multiple dice can be determined, and the bus training may be concluded, responsive to the combined feedback pattern matching the test pattern. The multiple dice may be stacked or linked.

Abstract: A method for fabricating semiconductor device includes forming an alternating stack that includes a lower multi-layered stack and an upper multi-layered stack by alternately stacking a dielectric layer and a sacrificial layer over a substrate, forming a vertical trench that divides the upper multi-layered stack into dummy stacks, and forming an asymmetric stepped trench that is extended downward from the vertical trench to divide the lower multi-layered stack into a pad stack and a dummy pad stack, wherein forming the asymmetric stepped trench includes forming a first stepped sidewall that is defined at an edge of the pad stack, and forming a second stepped sidewall that is defined at an edge of the dummy pad stack and occupies less area than the first stepped sidewall.

Abstract: Described apparatuses and methods provide automated error correction with memory refresh. Memory devices can include error correction code (ECC) technology to detect or correct one or more bit-errors in data. Dynamic random-access memory (DRAM), including low-power double data rate (LPPDR) synchronous DRAM (SDRAM), performs refresh operations to maintain data stored in a memory array. A refresh operation can be a self-refresh operation or an auto-refresh operation. Described implementations can combine ECC technology with refresh operations to determine a data error with data that is being refreshed or to correct erroneous data that is being refreshed. In an example, data for a read operation is checked for errors. If an error is detected, a corresponding address can be stored. Responsive to the corresponding address being refreshed, corrected data is stored at the corresponding address in conjunction with the refresh operation. Alternatively, data being refreshed can be checked for an error.