Abstract: A semiconductor probe having an embossed resistive tip and a method of fabricating the semiconductor probe are provided.

Abstract: A semiconductor probe with a high-resolution tip and a method of fabricating the same are provided. The semiconductor probe includes: a cantilever doped with a first impurity; a resistive convex portion projecting from an end portion of the cantilever and lightly doped with a second impurity opposite in polarity to the first impurity; and first and second electrode regions formed on either side of the resistive convex portion and heavily doped with the second impurity.

Abstract: A semiconductor probe with a high-resolution tip and a method of fabricating the same are provided. The semiconductor probe includes: a cantilever doped with a first impurity; a resistive convex portion projecting from an end portion of the cantilever and lightly doped with a second impurity opposite in polarity to the first impurity; and first and second electrode regions formed on either side of the resistive convex portion and heavily doped with the second impurity.

Abstract: A semiconductor probe and a method of fabricating the same are provided. The semiconductor probe includes a cantilever doped with first impurities, a resistive tip which protrudes from an end of the cantilever and doped lightly with second impurities, doping control layers formed on both sides of a protruding portion of the resistive tip, and first and second electrode regions formed under the doping control layers and doped heavily with the second impurities.

Abstract: A semiconductor probe with a high-resolution tip and a method of fabricating the same are provided. The semiconductor probe includes: a cantilever doped with a first impurity; a resistive convex portion projecting from an end portion of the cantilever and lightly doped with a second impurity opposite in polarity to the first impurity; and first and second electrode regions formed on either side of the resistive convex portion and heavily doped with the second impurity.

Abstract: A semiconductor probe with a resistive tip and a method of fabricating the semiconductor probe. The resistive tip doped with a first impurity includes a resistive region formed at a peak thereof and lightly doped with a second impurity opposite in polarity to the first impurity, and first and second semiconductor regions formed on sloped sides thereof and heavily doped with the second impurity. The semiconductor probe includes the resistive tip, a cantilever having an end on which the resistive tip is disposed, a dielectric layer disposed on the cantilever and covering the resistive region, and a metal shield disposed on the dielectric layer and having an opening formed at a position corresponding to the resistive region.

Abstract: The present invention provides a flash memory element and its manufacturing method having improved overall memory characteristics by constituting a double-gate element for improving the scaling down characteristic of flash memory element. With the above double-gate flash memory structure, a flash memory element in the present invention improves the scaling down characteristic and the programming and retention characteristic of a flash memory element.

Abstract: Field effect transistors include a semiconductor substrate having a channel region of first conductivity type therein extending adjacent a surface thereof. Source and drain regions of second conductivity type are also provided at opposite ends of the channel region. The source and drain regions extend in the semiconductor substrate and form P-N rectifying junctions with the channel region. A gate electrode extends on the channel region and comprises a first electrically conductive material having a first work function. A first sub-gate electrode extends on the channel region and comprises a second electrically conductive material having a second work function that is unequal to the first work function.

Abstract: Field effect transistors include a semiconductor substrate having a channel region of first conductivity type therein extending adjacent a surface thereof. Source and drain regions of second conductivity type are also provided at opposite ends of the channel region. The source and drain regions extend in the semiconductor substrate and form P-N rectifying junctions with the channel region. A gate electrode extends on the channel region and comprises a first electrically conductive material having a first work function. A first sub-gate electrode extends on the channel region and comprises a second electrically conductive material having a second work function that is unequal to the first work function.

Abstract: Field effect transistors include a semiconductor substrate having a channel region of first conductivity type therein extending adjacent a surface thereof. Source and drain regions of second conductivity type are also provided at opposite ends of the channel region. The source and drain regions extend in the semiconductor substrate and form P-N rectifying junctions with the channel region. A gate electrode extends on the channel region and comprises a first electrically conductive material having a first work function. A first sub-gate electrode extends on the channel region and comprises a second electrically conductive material having a second work function that is unequal to the first work function.

Abstract: A low power low noise amplifier achieves a high power gain without increasing power consumption by sharing the bias current. The amplifier is composed of a cascade structure which consists of a parallel connected common source transistor and common gate transistor connected to a common source transistor, an inverter type structure connected to the common source transistor, and structure improving the third-order intermodulation component using the parallel connected common source transistor and common gate transistor.

Abstract: The present invention provides a flash memory element and its manufacturing method having improved overall memory characteristics by constituting a double-gate element for improving the scaling down characteristic of flash memory element.

Abstract: The present invention relates to a low power low noise amplifier, more particularly to the low power low noise amplifier composed with low power by sharing the bias current.

Abstract: Disclosed is a method of fabricating an MOS transistor. The method comprises the following steps of: forming a gate pattern having a gate insulation film, main gate and a capping layer which are sequentially layered on a p-type semiconductor substrate; forming an isolating insulation film on the whole surface of a resultant structure having the gate pattern; forming a material layer for side gate on the isolating insulation film, the material layer having a work function smaller than those of the semiconductor substrate and the main gate; anisotropically etching the material layer for side gate and the isolating insulation film till the semiconductor substrate and the capping layer are exposed to form an isolating insulation pattern and side gate; respectively forming an n-type source/drain; and forming a conductive film pattern on the resultant structure, the conductive film electrically connecting the source to the adjacent side gate or the drain to the adjacent side gate.

Abstract: A temperature-adaptive capacitor array used in a TCXO so that the TCXO effectively conducts temperature-compensating in the resonant frequency without the non-monotonicity while a smaller silicon area is used in producing the capacitor array. A number of capacitor arrays allocated in two capacitor banks. Each of the capacitor arrays comprises two or more unit cells, and in turn each unit cell consists of a unit capacitor and a switching element, respectively. All of unit capacitors included in the capacitor arrays are connected each other through a decoder assembly to provide a crystal oscillator with a load capacitance. The unit capacitors belonging to one of the capacitor arrays have the same capacitance with each other. Two unit capacitors belonging to different capacitor arrays, however, have different capacitances from each other.

Abstract: The present invention proposes a method for fabricating a non-volatile memory device using nano-crystals with an increased etching rate and an increased oxidation rate at the grain boundary, which is used in high-speed and low power consumption device. The method for fabricating a non-volatile memory device using nano-crystal dots comprises following processes. First process is to fabricate a tunneling dielectric 204 and a thin amorphous silicon continuous film. Second process is to fabricate a poly-silicon layer by poly-crystallizing the amorphous silicon film. Third process is to fabricate nano-crystals 212 by etching the poly-silicon layer. Fourth process is to fabricate an interlayer dielectric 214 on the nano-crystals 212. Fifth process is to attach a poly-silicon film to the interlayer dielectric 214 and fabricate a gate 216 and interconnects 220.