Abstract: A system and a method are disclosed for changing a filter provided in an air purifier at an optimum time by measuring the rotational speed of a motor that operates the filter. The system for determining an air purifier filter change time includes: a motor speed measurement unit; a time counting unit; a speed determination unit; a time comparison unit; and a filter change time determination unit.

Abstract: A method of performing a read operation on nonvolatile memory device comprises receiving a read command, receiving addresses, detecting a transition of a read enable signal, generating a strobe signal based on the transition of the read enable signal, reading data corresponding to the received addresses, and outputting the read data after the strobe signal is toggled a predetermined number of times.

Abstract: Multiple bits are programmed in a NAND flash memory device by programming a memory cell with an LSB; storing the LSB into a cache register from the memory cell; programming the memory cell with an MSB that is stored in a main register; storing a data bit into the main register from the memory cell during a first verifying operation; storing a data bit into the cache register from the memory cell during a second verifying operation; and transferring the data bit to the main register from the cache register.

Abstract: A portable terminal is formed with reinforced structures for withstanding external impacts. The portable terminal includes a front case and an input device arranged on the front case. A first rear cover coupled to a rear side of the front case is formed from a metallic material. A second rear cover coupled to the rear side of the front case and the first rear cover is formed from a synthetic resin. And a fastening device anchors the second rear cover to the rear side of the front case. The input device is positioned on an outer surface of the front case, and the fastening device is anchored to a rear side of the input device.

Abstract: A flash memory device includes a word line decoder configured to receive a row address, and decode a selected word line and a neighboring non-selected word line corresponding to the row address during a read operation, and a word line driver configured to receive data identifying the selected word line and the neighboring non-selected word line from the word line decoder, and applying a read voltage to the selected word line, a first voltage to non-selected word lines other than the neighboring non-selected word line, and a second voltage to the neighboring non-selected word line.

Abstract: A nonvolatile memory device includes an array of memory cells arranged in rows and columns, the array of memory cells having wordlines associated therewith. A wordline voltage controller determines the levels of wordline voltages to be supplied to the respective wordlines and a wordline voltage generator generates the wordline voltages at the determined levels. Related methods are also provided.

Abstract: A non-volatile memory device may include a memory cell array, a page buffer, a column decoder, a column selection circuit and a repair circuit. The memory cell array includes normal memory cells and redundancy memory cells. In one example, the page buffer may load normal data and redundancy data from the memory cell array. The column decoder may generate a normal column selection signal and a redundancy column selection signal in response to a column address. The column selection circuit may select the normal data and redundancy data in response to the normal column selection signal and redundancy column selection signal. The repair circuit may then output one of the normal data and redundancy data.

Abstract: The present disclosure relates to insert sheets and a method for manufacturing same. A film of the present invention is applicable to a variety of insert moldings or injection moldings to achieve appearance effects such as an excellent metal texture and the like, and maintain excellence in the overall physical properties such as surface properties, formability, scratch resistance, impact resistance, heat resistance, wear resistance, chemical resistance, and light resistance, etc.

Abstract: A method and apparatus control power consumption in a portable terminal by cutting the direct current (DC) bias voltage. The power consumption control apparatus of a portable terminal is connected to the processors. The apparatus includes an oscillator, an inverter, and a DC bias voltage cutting unit. The oscillator creates signals to control the portable terminal to be operated in a sleep mode or a standby mode. The inverter receives the signals from the oscillator and outputs inverted signals to the processors. The DC bias voltage cutting unit cuts a DC bias voltage that is derived on a feedback line between an input port and an output port of the inverter, from the signals created by the oscillator. The apparatus and method can allow the portable terminal to reduce the power consumption when the processors are driven.

Abstract: A nonvolatile memory device includes an array of memory cells arranged in rows and columns, the array of memory cells having wordlines associated therewith. A wordline voltage controller determines the levels of wordline voltages to be supplied to the respective wordlines and a wordline voltage generator generates the wordline voltages at the determined levels. Related methods are also provided.

Abstract: A nonvolatile memory device includes an array of memory cells arranged in rows and columns, the array of memory cells having wordlines associated therewith. A wordline voltage controller determines the levels of wordline voltages to be supplied to the respective wordlines and a wordline voltage generator generates the wordline voltages at the determined levels. Related methods are also provided.

Abstract: A memory device includes a main memory cell array and a redundant memory cell array configured to store a first parity code for data stored in the main memory cell array. The device further includes a parity generator configured to generate a second parity code responsive to reading of the stored data from the main memory cell array, and a comparator configured to compare the first and second parity codes. In some embodiments, the parity generator configured to generate the second parity code during a copyback operation.

Abstract: A NAND flash memory device performing an error detecting and data reloading operation during a copy back program operation is provided. The device includes a cell array having a plurality of planes and a parity cell array having a plurality of parity planes. Each of the parity planes stores a parity of each of the planes. Additionally, the device includes a parity generating and parity column selecting circuit generating a new parity about reloaded data from an outside during a copy back program operation, and storing the new parity on a parity plane corresponding to a plane on which the reloaded data is stored.

Abstract: A flash memory device includes a word line decoder configured to receive a row address, and decode a selected word line and a neighboring non-selected word line corresponding to the row address during a read operation, and a word line driver configured to receive data identifying the selected word line and the neighboring non-selected word line from the word line decoder, and applying a read voltage to the selected word line, a first voltage to non-selected word lines other than the neighboring non-selected word line, and a second voltage to the neighboring non-selected word line.

Abstract: A system and method for changing a filter provided in an air purifier at an optimum time by measuring the rotational speed of a motor that operates the filter.

Abstract: Disclosed is a program method of a non-volatile memory device. The program method includes performing a least significant bit (LSB) program operation, during which an LSB program number is stored, and performing a most significant bit (MSB) program operation in a threshold voltage state order determined according to the LSB program number.

Abstract: Disclosed is an operating method of a flash memory device, which includes normal memory cells and dummy memory cells. The operating method includes programming the normal memory cells and programming the dummy memory cells. A dummy pass voltage used for programming the dummy memory cells is different from a normal pass voltage used for programming the normal memory cells.

Abstract: A nonvolatile semiconductor memory device includes a fuse, a switching enable circuit to generate a switching enable signal in response to a state of the fuse, and a switching unit to couple an internal output line of a page buffer set to a global output line in response to the switching enable signal.

Abstract: A bit failure detection circuit supports reliability testing of a memory device by accumulating a sum of data errors in data read from the memory device. The detection circuit compares a plurality of bytes of data read from the memory device against a plurality of bytes of reference data supplied during a test operation. The detection circuit also generates a flag upon detection that the sum of data errors exceeds a threshold number of acceptable data errors.

Abstract: Multiple bits are programmed in a NAND flash memory device by programming a memory cell with an LSB; storing the LSB into a cache register from the memory cell; programming the memory cell with an MSB that is stored in a main register; storing a data bit into the main register from the memory cell during a first verifying operation; storing a data bit into the cache register from the memory cell during a second verifying operation; and transferring the data bit to the main register from the cache register.