Abstract: A NAND flash memory device according to some embodiments includes a cell array, a page buffer configured to copyback read the data in the cell array, and an error detector for detecting errors that occur during the copyback reading and for generating a detection signal. Detecting errors is performed concurrently with a copyback program operation and completes before finishing a copyback program verify operation. The data stored in the page buffer may be copyback programmed when the detection signal is a pass signal. The copyback operation may end without executing the copyback program operation when the detection signal is a fail signal. Since the copyback program operation and the error detection operation are performed concurrently, the errors occurring during the copyback operation may be detected without additional time delay. Additionally, occurrence of two-bit error may be prevented because the copyback program is not executed when the fail signal is generated.

Abstract: A nonvolatile memory device includes an array of memory cells arranged in rows and columns, the array of memory cells having wordlines associated therewith. A wordline voltage controller determines the levels of wordline voltages to be supplied to the respective wordlines and a wordline voltage generator generates the wordline voltages at the determined levels. Related methods are also provided.

Abstract: Multiple bits are programmed in a NAND flash memory device by programming a memory cell with an LSB; storing the LSB into a cache register from the memory cell; programming the memory cell with an MSB that is stored in a main register; storing a data bit into the main register from the memory cell during a first verifying operation; storing a data bit into the cache register from the memory cell during a second verifying operation; and transferring the data bit to the main register from the cache register.

Abstract: A wireless LAN system and a method of using the same. The wireless LAN system includes at least one Interface Service Commercial module (ISCM) for collecting and transferring channel information related to channels in use for wireless networks located in a neighboring area; and an Access Point (AP) having a module for adjusting an established channel to a different frequency band channel based on a comparison result of the transferred channel information and the currently established channel. Accordingly, the wireless LAN system prevents crosstalk and interference with different LAN systems existing in a neighboring area to improve the efficiency of a wireless LAN system.

Abstract: The present invention relates to an electric radiating pipe capable of enhancing a heating efficiency in such a manner that a mixture of a porous operation medium and a volatile operation fluid is filled in a radiation pipe, and a porous operation medium is fast heated based on a viscosity difference, and a densely filled operation fluid is phase-changed to a high temperature vapor or a high temperature liquid based on a heated operation medium. In a radiating pipe that includes a certain shaped pipe body, and a heat wire passing through to the interior of the pipe body wherein both ends of the pipe body are sealed by a plugging cap, there is provided an electric radiating pipe that includes a porous non-flammable operation medium and volatile operation fluid being mixed and being filled into the interior of the pipe body.

Abstract: A nonvolatile memory device includes an array of memory cells arranged in rows and columns, the array of memory cells having wordlines associated therewith. A wordline voltage controller determines the levels of wordline voltages to be supplied to the respective wordlines and a wordline voltage generator generates the wordline voltages at the determined levels. Related methods are also provided.

Abstract: A NAND flash memory device performing an error detecting and data reloading operation during a copy back program operation is provided. The device includes a cell array having a plurality of planes and a parity cell array having a plurality of parity planes. Each of the parity planes stores a parity of each of the planes. Additionally, the device includes a parity generating and parity column selecting circuit generating a new parity about reloaded data from an outside during a copy back program operation, and storing the new parity on a parity plane corresponding to a plane on which the reloaded data is stored.

Abstract: Multiple bits are programmed in a NAND flash memory device by programming a memory cell with an LSB; storing the LSB into a cache register from the memory cell; programming the memory cell with an MSB that is stored in a main register; storing a data bit into the main register from the memory cell during a first verifying operation; storing a data bit into the cache register from the memory cell during a second verifying operation; and transferring the data bit to the main register from the cache register. Related devices are also disclosed.

Abstract: A home network system and a method of providing information in the home network system, wherein the home network system includes a sensor network tracking the location of a user in real time and transmitting location information of the user, a plurality of information terminals providing predetermined information to the user, and a home server receiving the location information from the sensor network and transmitting the predetermined information to the user, by selecting at least one of the plurality of information terminals by using the location information.

Abstract: A nonvolatile memory device includes an array of memory cells arranged in rows and columns, the array of memory cells having wordlines associated therewith. A wordline voltage controller determines the levels of wordline voltages to be supplied to the respective wordlines and a wordline voltage generator generates the wordline voltages at the determined levels. Related methods are also provided.

Abstract: A bit failure detection circuit supports reliability testing of a memory device by accumulating a sum of data errors in data read from the memory device. The detection circuit compares a plurality of bytes of data read from the memory device against a plurality of bytes of reference data supplied during a test operation. The detection circuit also generates a flag upon detection that the sum of data errors exceeds a threshold number of acceptable data errors.

Abstract: The present invention relates to an electric radiating pipe capable of enhancing a heating efficiency in such a manner that a mixture of a porous operation medium and a volatile operation fluid is filled in a radiation pipe, and a porous operation medium is fast heated based on a viscosity difference, and a densely filled operation fluid is phase-changed to a high temperature vapor or a high temperature liquid based on a heated operation medium. In a radiating pipe that includes a certain shaped pipe body, and a heat wire passing through to the interior of the pipe body wherein both ends of the pipe body are sealed by a plugging cap, there is provided an electric radiating pipe that includes a porous inflammable operation medium and volatile operation fluid being mixed and being filled into the interior of the pipe body.

Abstract: A NAND flash memory device according to some embodiments includes a cell array, a page buffer configured to copyback read the data in the cell array, and an error detector for detecting errors that occur during the copyback reading and for generating a detection signal. Detecting errors is performed concurrently with a copyback program operation and completes before finishing a copyback program verify operation. The data stored in the page buffer may be copyback programmed when the detection signal is a pass signal. The copyback operation may end without executing the copyback program operation when the detection signal is a fail signal. Since the copyback program operation and the error detection operation are performed concurrently, the errors occurring during the copyback operation may be detected without additional time delay. Additionally, occurrence of two-bit error may be prevented because the copyback program is not executed when the fail signal is generated.

Abstract: A memory device includes a main memory cell array and a redundant memory cell array configured to store a first parity code for data stored in the main memory cell array. The device further includes a parity generator configured to generate a second parity code responsive to reading of the stored data from the main memory cell array, and a comparator configured to compare the first and second parity codes. The parity generator may be configured to generate the second parity code during a copyback operation.

Abstract: A wireless LAN system and a method of using the same. The wireless LAN system includes at least one Interface Service Commercial module (ISCM) for collecting and transferring channel information related to channels in use for wireless networks located in a neighboring area; and an Access Point (AP) having a module for adjusting an established channel to a different frequency band channel based on a comparison result of the transferred channel information and the currently established channel. Accordingly, the wireless LAN system prevents crosstalk and interference with different LAN systems existing in a neighboring area to improve the efficiency of a wireless LAN system.

Abstract: A semiconductor memory device has at least one data line, registers for storing data bits, and switch elements corresponding to the registers for transferring the data bits to the data line in response to corresponding selection signals. It also has a precharge circuit connected to the data line, for precharging the data line to a power supply voltage in response to a precharge control signal. The selection signals are sequentially activated at a predetermined time interval by synchronously responding to a clock signal, and the precharge control signal is activated during the interval of the selection signals, by synchronously responding to the clock signal.

Abstract: A semiconductor memory device includes a select signal generator, a wordline voltage generator, and a switch circuit. During a test operation mode, the device determine whether a wordline voltage has required level. The select signal generator activates one of select signals each corresponding to the other wordline voltages responsive to external select code signals. The external select code signals appoint an external instruction signal representative and appoint other wordline voltages used in the memory device. The wordline voltage generator generates a wordline voltage corresponding to the activated select signal out. The switch circuit transfers the wordline voltage outputted from the wordline voltage generator to a pad connected to an external pin.

Abstract: A semiconductor memory device includes a select signal generator, a wordline voltage generator, and a switch circuit. During a test operation mode, the device determines whether a wordline voltage has required level. The select signal generator activates one of select signals each corresponding to the other wordline voltages responsive to external select code signals. The external select code signals appoint an external instruction signal representative and appoint other wordline voltages used in the memory device. The wordline voltage generator generates a wordline voltage corresponding to the activated select signal out. The switch circuit transfers the wordline voltage outputted from the wordline voltage generator to a pad connected to an external pin.

Abstract: A semiconductor memory device has at least one data line, registers for storing data bits, and switch elements corresponding to the registers for transferring the data bits to the data line in response to corresponding selection signals. It also has a precharge circuit connected to the data line, for precharging the data line to a power supply voltage in response to a precharge control signal. The selection signals are sequentially activated at a predetermined time interval by synchronously responding to a clock signal, and the precharge control signal is activated during the interval of the selection signals, by synchronously responding to the clock signal.