Abstract: A gene amplification chip includes a chamber layer, a cover layer, a bottom layer, an inlet, and an outlet. The chamber layer has a first passage and through holes which are formed on one side of the first passage. The cover layer is disposed on one side of the chamber layer and has a cover channel formed to communicate with the first passage and the through holes, wherein the cover channel, the first passage and the through holes allow passage of liquids in a divided manner. The bottom layer is disposed on another side of the chamber layer and has a bottom channel formed to communicate with the first passage and the through holes. The inlet is formed in the cover layer and communicates with the cover channel. The outlet communicates with any one of the cover channel and the bottom channel.

Abstract: A method of manufacturing a multilayer metal plate by electroplating includes a first forming operation of forming one of a first metal layer and a second metal layer on a substrate by electroplating, wherein the second metal layer is less recrystallized than the first metal layer, the second metal layer is comprised of nanometer-size grains, and the second metal layer has a higher level of tensile strength than the first metal layer; and a second forming operation of forming, by electroplating, a third metal layer not formed in the first forming operation on a surface of one of the first metal layer and the second metal layer formed in the first forming operation.

Abstract: A semiconductor device includes a source/drain region in a fin-type active pattern, a gate structure adjacent to the source/drain region, and an insulating layer on the source/drain region and the gate structure. A shared contact plug penetrates through the insulating layer and includes a first lower portion connected to the source/drain region, a second lower portion connected to the gate structure, and an upper portion connected to upper surfaces of the first lower portion and the second lower portion. A plug spacer film is between the insulating layer and at least one of the first lower portion and the second lower portion and includes a material different from a material of the insulating layer.

Abstract: A method for automatically generating blank-space inference questions for a foreign language sentence, according to the present invention, comprises the steps of: receiving one or more foreign language sentence; designating a range to be set as blank spaces among the inputted foreign language sentences; designating setting information for generating a wrong-answer sheet; and generating blank-space inference questions according to the blank range and the setting information by using a sentence generation algorithm based on preset artificial intelligence.

Abstract: A semiconductor device includes a first active pattern on a substrate. The first active pattern includes a pair of first source/drain patterns and a first channel pattern therebetween. A gate electrode is disposed on the first channel pattern, and a first gate spacer is disposed on a side surface of the gate electrode. The first gate spacer includes a first spacer and a second spacer. A top surface of the first spacer is lower than a top surface of the second spacer. A first blocking pattern is disposed on the first spacer, and a gate contact is coupled to the gate electrode. The first blocking pattern is interposed between the gate contact and the second spacer.

Abstract: A semiconductor device includes a source/drain region in a fin-type active pattern, a gate structure adjacent to the source/drain region, and an insulating layer on the source/drain region and the gate structure. A shared contact plug penetrates through the insulating layer and includes a first lower portion connected to the source/drain region, a second lower portion connected to the gate structure, and an upper portion connected to upper surfaces of the first lower portion and the second lower portion. A plug spacer film is between the insulating layer and at least one of the first lower portion and the second lower portion and includes a material different from a material of the insulating layer.

Abstract: A semiconductor device includes a source/drain region in a fin-type active pattern, a gate structure adjacent to the source/drain region, and an insulating layer on the source/drain region and the gate structure. A shared contact plug penetrates through the insulating layer and includes a first lower portion connected to the source/drain region, a second lower portion connected to the gate structure, and an upper portion connected to upper surfaces of the first lower portion and the second lower portion. A plug spacer film is between the insulating layer and at least one of the first lower portion and the second lower portion and includes a material different from a material of the insulating layer.

Abstract: Disclosed is a semiconductor device including a first active pattern and a second active pattern that extend in a first direction on a substrate and are spaced apart from each other in a second direction crossing the first direction, a first gate structure that extends across the first and second active patterns, a second gate structure that is spaced apart from the first gate structure, and a node contact between the first and second gate structures that electrically connects the first active pattern and the second active pattern to each other. The node contact comprises a first end adjacent to the first active pattern and a second end adjacent to the second active pattern. The second end of the node contact being shifted in the first direction relative to the first end of the node contact so as to be closer to the second gate structure than to the first gate structure.

Abstract: The present invention relates to a photocurable resin composition usable in a nanoimprint process which is capable of overcoming low productivity of conventional semiconductor processes for optical devices and electronic devices, and a method of forming patterns using the same. Specifically, the present invention relates to a photocurable resin composition including a specific perfluorinated acrylic compound for improving release property between a nanoimprint mold and the photocurable resin composition, and a method of forming patterns using the same.

Abstract: The present invention relates to an adhesive composition capable of improving adhesion force between two interfaces through thermal crosslinking and photo-crosslinking of a substrate and a resin, or a resin and a resin, in processes for optical devices and electronic devices, and a preparation method thereof. Specifically, the present invention relates to an adhesive composition capable of adhering an interface between a substrate and a photocurable resin, and a method of adhering an interface using the same.

Abstract: Bioconjugation methods for promoting wound healing are disclosed. In particular, the invention relates to the in situ application of non-photochemical crosslinking techniques such as copper-free click chemistry using strain-promoted azide-alkyne cycloaddition (SPAAC) or multi-functional succinimidyl esters as a therapeutic delivery modality for biomolecules and stem cells to enhance wound healing.

Abstract: A semiconductor device includes a substrate including active patterns, a device isolation layer filling a trench between a pair of adjacent active patterns, a gate electrode on the active patterns, and a gate contact on the gate electrode. Each active pattern includes source/drain patterns at opposite sides of the gate electrode. The gate contact includes a first portion vertically overlapping with the gate electrode, and a second portion laterally extending from the first portion such that the second portion vertically overlaps with the device isolation layer and does not vertically overlap with the gate electrode. A bottom surface of the second portion is distal to the substrate in relation to a bottom surface of the first portion. The bottom surface of the second portion is distal to the substrate in relation to a top of a source/drain pattern that is adjacent to the second portion.

Abstract: A semiconductor device includes a lower interlayer insulating film including a first trench and a second trench adjacent each other; a first gate structure within the first trench and extending in a first direction; a second gate structure within the second trench and extending in the first direction; a source/drain adjacent the first gate structure and the second gate structure; an upper interlayer insulating film on the lower interlayer insulating film; and a contact connected to the source/drain, the contact in the upper interlayer insulating film and the lower interlayer insulating film, wherein the contact includes a first side wall and a second side wall, the first side wall of the contact and the second side wall of the contact are asymmetric with each other, and the contact does not vertically overlap the first gate structure and the second gate structure.

Abstract: A semiconductor device includes a source/drain region in a fin-type active pattern, a gate structure adjacent to the source/drain region, and an insulating layer on the source/drain region and the gate structure. A shared contact plug penetrates through the insulating layer and includes a first lower portion connected to the source/drain region, a second lower portion connected to the gate structure, and an upper portion connected to upper surfaces of the first lower portion and the second lower portion. A plug spacer film is between the insulating layer and at least one of the first lower portion and the second lower portion and includes a material different from a material of the insulating layer.

Abstract: The inventive concepts relate to a semiconductor device including a field effect transistor and a method for manufacturing the same. The semiconductor device includes a substrate including first and second source/drain regions formed thereon, a gate electrode intersecting the substrate between the first and second source/drain regions, and an active contact electrically connecting the first and second source/drain regions to each other. The active contact is spaced apart from the gate electrode. The active contact includes first sub-contacts provided on the first and second source/drain regions so as to be connected to the first and second source/drain regions, respectively, a second sub-contact provided on the first sub-contacts to electrically connect the first sub-contacts to each other, and a barrier layer provided between the second sub-contact and each of the first sub-contacts.

Abstract: Disclosed is a semiconductor device including a first active pattern and a second active pattern that extend in a first direction on a substrate and are spaced apart from each other in a second direction crossing the first direction, a first gate structure that extends across the first and second active patterns, a second gate structure that is spaced apart from the first gate structure, and a node contact between the first and second gate structures that electrically connects the first active pattern and the second active pattern to each other. The node contact comprises a first end adjacent to the first active pattern and a second end adjacent to the second active pattern. The second end of the node contact being shifted in the first direction relative to the first end of the node contact so as to be closer to the second gate structure than to the first gate structure.

Abstract: A semiconductor device includes a source/drain region in a fin-type active pattern, a gate structure adjacent to the source/drain region, and an insulating layer on the source/drain region and the gate structure. A shared contact plug penetrates through the insulating layer and includes a first lower portion connected to the source/drain region, a second lower portion connected to the gate structure, and an upper portion connected to upper surfaces of the first lower portion and the second lower portion. A plug spacer film is between the insulating layer and at least one of the first lower portion and the second lower portion and includes a material different from a material of the insulating layer.

Abstract: A semiconductor device includes a substrate including active patterns, a device isolation layer filling a trench between a pair of adjacent active patterns, a gate electrode on the active patterns, and a gate contact on the gate electrode. Each active pattern includes source/drain patterns at opposite sides of the gate electrode. The gate contact includes a first portion vertically overlapping with the gate electrode, and a second portion laterally extending from the first portion such that the second portion vertically overlaps with the device isolation layer and does not vertically overlap with the gate electrode. A bottom surface of the second portion is distal to the substrate in relation to a bottom surface of the first portion. The bottom surface of the second portion is distal to the substrate in relation to a top of a source/drain pattern that is adjacent to the second portion.

Abstract: A semiconductor device includes a lower interlayer insulating film including a first trench and a second trench adjacent each other; a first gate structure within the first trench and extending in a first direction; a second gate structure within the second trench and extending in the first direction; a source/drain adjacent the first gate structure and the second gate structure; an upper interlayer insulating film on the lower interlayer insulating film; and a contact connected to the source/drain, the contact in the upper interlayer insulating film and the lower interlayer insulating film, wherein the contact includes a first side wall and a second side wall, the first side wall of the contact and the second side wall of the contact are asymmetric with each other, and the contact does not vertically overlap the first gate structure and the second gate structure.

Abstract: A semiconductor device, including first and second fin patterns separated by a first trench; a gate electrode intersecting the first and second fin patterns; and a contact on at least one side of the gate electrode, the contact contacting the first fin pattern, the contact having a bottom surface that does not contact the second fin pattern, a height from a bottom of the first trench to a topmost end of the first fin pattern in a region in which the contact intersects the first fin pattern being a first height, and a height from the bottom of the first trench to a topmost end of the second fin pattern in a region in which an extension line of the contact extending along a direction in which the gate electrode extends intersects the second fin pattern being a second height, the first height being smaller than the second height.