Abstract: A memory system includes a plurality of memory cells at intersections between a plurality of word lines and a plurality of bit lines, and a plurality of bit line sense amplifiers connected to the plurality of bit lines, the plurality of bit line sense amplifiers configured to write data to or read data from the plurality of memory cells through the plurality of bit lines, a redundancy bit line sense amplifier among the plurality of bit line sense amplifiers configured to generate a physically unclonable function (PUF) key including a unique random digital value.

Abstract: Disclosed are an apparatus for distributing power of an electric vehicle and a method thereof capable of optimally improving the energy consumption efficiency of the electric vehicle by predicting a vehicle speed for a predetermined time using a learned vehicle speed prediction model, determining wheel power based on the vehicle speed, and distributing the wheel power to a front wheel drive motor and a rear wheel drive motor. The apparatus includes a storage that stores a vehicle speed prediction model in which learning is completed, and a controller that predicts a vehicle speed for a preset time using the vehicle speed prediction model, determines wheel power based on the vehicle speed, and distributes the wheel power to a front wheel drive motor and a rear wheel drive motor.

Abstract: The present invention discloses a system and method for redesigning treatment prescriptions according to evaluation of treatment effectiveness. In the present invention, when the system receives the treatment prescriptions from the medical staff terminal, sets the treatment device according to the treatment prescriptions, and delivers the treatment device to the patient, the patient performs treatment by himself using the treatment device at home. When the treatment is finished, the patient terminal transmits the treatment history information, the treatment image obtained by photographing the process of self-treatment, and the questionnaire replies to the system. The system calculates compliance from the treatment history information, evaluates the treatment motor/cognitive/emotional functions from the questionnaire reply, and then provides them to the medical staff terminal together with the questionnaire replies, and allows the medical staff to evaluate effect of the treatment prescriptions.

Abstract: A storage device may include a one time programmable (OTP) memory including a plurality of OTP cells and configured to store OTP key values in the plurality of OTP cells, and an erase instruction circuit that is detachably mounted on the storage device and connected to a first node of the OTP memory. When the erase instruction circuit is removed from the storage device, the OTP memory may be configured to receive the erase instruction signal having a first logic level at the first node and permanently erase all the OTP key values stored in the plurality of OTP cells by programming the plurality of OTP cells to an identical OTP key value in response to the erase instruction signal having the first logic level.

Abstract: A storage device may include a one time programmable (OTP) memory including a plurality of OTP cells and configured to store OTP key values in the plurality of OTP cells, and an erase instruction circuit that is detachably mounted on the storage device and connected to a first node of the OTP memory. When the erase instruction circuit is removed from the storage device, the OTP memory may be configured to receive the erase instruction signal having a first logic level at the first node and permanently erase all the OTP key values stored in the plurality of OTP cells by programming the plurality of OTP cells to an identical OTP key value in response to the erase instruction signal having the first logic level.

Abstract: A memory system includes a plurality of memory cells at intersections between a plurality of word lines and a plurality of bit lines, and a plurality of bit line sense amplifiers connected to the plurality of bit lines, the plurality of bit line sense amplifiers configured to write data to or read data from the plurality of memory cells through the plurality of bit lines, a redundancy bit line sense amplifier among the plurality of bit line sense amplifiers configured to generate a physically unclonable function (PUF) key including a unique random digital value.

Abstract: Described is a method and apparatus for compensating for a change in an output characteristic of a temperature sensor due to varying temperature. The temperature sensor includes a temperature sensing core, an analog-to-digital converter, a counter, and a temperature compensating circuit. The temperature sensing core generates a sense voltage corresponding to a sensed temperature. The analog-to-digital converter converts the sense voltage into a digital signal and generates a conversion signal. The temperature compensating circuit generates a counter clock signal that varies according to a temperature change. The counter counts the number of pulses of the counter clock signal according to the conversion signal.

Abstract: A semiconductor memory device adjusts a timing interval between the activation of first and second amplifiers in a sense amplifier circuit based on the distance between the sense amplifier circuit and corresponding power supply.

Abstract: The semiconductor memory device includes a first memory cell connected between a first word line and a bit line. The semiconductor memory device may also include a second memory cell connected between a second word line and an inverted bit line. Additionally, the memory device may include a precharger configured to charge the bit line and the inverted bit line to a first voltage before a read operation, a first sense amplifier having a first transistor connected between to the bit line and a first node, the first transistor including a gate to which a signal of the inverted bit line is applied.

Abstract: A semiconductor device includes a data line pair formed of a data line and a complementary data line; a first sensing amplification unit including a first sensing amplifier and a second sensing amplifier that are cross-coupled with the data line and the complementary data line; a first variable current source supplying or flowing out a first variable current to the first sensing amplifier; and a second variable current source supplying or flowing out a second variable current to the second sensing amplifier. A current amount of the first variable current is different from a current amount of the second variable current.

Abstract: A semiconductor device includes an alternating arrangement of memory cell blocks and sense amplifier blocks, such that the sense amplifier blocks include an interior sense amplifier block and a periphery amplifier block. The peripheral amplifier block includes a first sense amplification unit having a first sense amplifier and a second sense amplifier cross-coupled between a bit line and a complementary bit line. The first sense amplifier supplies/receives current to/from the bit line, the second sense amplifier provides/receives current to/from the complementary bit line, and a current driving capability for the first sense amplifier is greater than a current driving capability of the second sense amplifier.

Abstract: A semiconductor memory device adjusts a timing interval between the activation of first and second amplifiers in a sense amplifier circuit based on the distance between the sense amplifier circuit and corresponding power supply.

Abstract: The semiconductor memory device includes a first memory cell connected between a first word line and a bit line. The semiconductor memory device may also include a second memory cell connected between a second word line and an inverted bit line. Additionally, the memory device may include a precharger configured to charge the bit line and the inverted bit line to a first voltage before a read operation, a first sense amplifier having a first transistor connected between to the bit line and a first node, the first transistor including a gate to which a signal of the inverted bit line is applied.

Abstract: Described is a method and apparatus for compensating for a change in an output characteristic of a temperature sensor due to varying temperature. The temperature sensor includes a temperature sensing core, an analog-to-digital converter, a counter, and a temperature compensating circuit. The temperature sensing core generates a sense voltage corresponding to a sensed temperature. The analog-to-digital converter converts the sense voltage into a digital signal and generates a conversion signal. The temperature compensating circuit generates a counter clock signal that varies according to a temperature change. The counter counts the number of pulses of the counter clock signal according to the conversion signal.

Abstract: Delay circuits are provided. Some embodiments of delay circuits herein include a delay line including multiple delay cells connected in series and a variable voltage supplier operative to output a voltage value proportional and/or inversely proportional to a temperature. Delay circuits may include at least one loading capacitor that includes a first end that is connected to an output port of the delay cell and a second end that is connected to an output port of the variable voltage supplier, the at least one loading capacitor including a capacitance that is decreased corresponding to an increase in temperature when a positive voltage is applied across the first end and the second end of the at least one loading capacitor.

Abstract: A semiconductor device includes an alternating arrangement of memory cell blocks and sense amplifier blocks, such that the sense amplifier blocks include an interior sense amplifier block and a periphery amplifier block. The peripheral amplifier block includes a first sense amplification unit having a first sense amplifier and a second sense amplifier cross-coupled between a bit line and a complementary bit line. The first sense amplifier supplies/receives current to/from the bit line, the second sense amplifier provides/receives current to/from the complementary bit line, and a current driving capability for the first sense amplifier is greater than a current driving capability of the second sense amplifier.

Abstract: Example embodiments are directed to an apparatus and method for measuring a pulse width. A side-band signal generator may be configured to receive a given data pattern and output a side-band signal by modulating a pulse width of the received data pattern in a test mode. A phase detector may be configured to receive the side-band signal and a reference clock signal, and output a pulse signal corresponding to a phase difference between the received side-band signal and the reference clock signal. A charge pump may be configured to receive the pulse signal and output an output voltage by increasing or decreasing the output voltage based on the pulse signal. A pulse width measurer may be configured to receive the output voltage of the charge pump and determine whether pulses forming the side-band signal have appropriate widths based on whether the output voltage is included in a desired reference voltage range.

Abstract: A semiconductor device includes a data line pair formed of a data line and a complementary data line; a first sensing amplification unit including a first sensing amplifier and a second sensing amplifier that are cross-coupled with the data line and the complementary data line; a first variable current source supplying or flowing out a first variable current to the first sensing amplifier; and a second variable current source supplying or flowing out a second variable current to the second sensing amplifier. A current amount of the first variable current is different from a current amount of the second variable current.

Abstract: A temperature sensing circuit includes first, second and third proportional to absolute temperature (PTAT) units, and first and second subtracters. The first PTAT unit generates a first output voltage based on a reference current and a current of N times the reference current, where N is an emitter current density ratio. The second PTAT unit generates a second output voltage based on a current of twice the reference current and a current of 2N times the reference current. The third PTAT unit generates a third output voltage based on the reference current and a current of N times the reference current. The first subtracter performs subtraction on the second output voltage and the third output voltage, and the second subtracter performs subtraction on an output voltage of the first subtracter and the first output voltage.

Abstract: Delay circuits are provided. Some embodiments of delay circuits herein include a delay line including multiple delay cells connected in series and a variable voltage supplier operative to output a voltage value proportional and/or inversely proportional to a temperature. Delay circuits may include at least one loading capacitor that includes a first end that is connected to an output port of the delay cell and a second end that is connected to an output port of the variable voltage supplier., the at least one loading capacitor including a capacitance that is decreased corresponding to an increase in temperature when a positive voltage is applied across the first end and the second end of the at least one loading capacitor.