Abstract: Provided are an organic electronic element comprising an anode, a cathode, and an organic material layer between the anode and the cathode, and an electronic device comprising the organic electronic element, wherein the organic material layer comprises each compound represented by Formula 1, Formula 2, or Formula 3, thereby the driving voltage of the organic electronic element can be lowered and the luminous efficiency and lifespan can be improved.

Abstract: Provided are an organic electronic element comprising an anode, a cathode, and an organic material layer between the anode and the cathode, and an electronic device comprising the organic electronic element, wherein the organic material layer comprises each compound represented by Formula 1, Formula 2, or Formula 3, thereby the driving voltage of the organic electronic element can be lowered and the luminous efficiency and lifespan can be improved.

Abstract: The present invention relates to a biodegradable polyester resin, in which the first repeat unit comprising a first diol residue and an aromatic dicarboxylic acid residue and the second repeat unit comprising a second diol residue and an aliphatic dicarboxylic acid residue satisfy a ratio of the number of repeat units in a specific range, and the softness index of the resin satisfies a specific range, and to a process for preparing the same. Since the biodegradable polyester resin can provide a biodegradable polyester sheet or film that can be simultaneously enhanced in productivity, processability, and moldability and is excellent in tensile strength, tear strength, and friction coefficient and excellent in biodegradability and water degradability, it can be utilized in more diverse fields.

Abstract: Embodiments relate to a biodegradable and polymerizable polyester composition, to a biodegradable polyester resin prepared therefrom, and to a process for preparing the same. As the biodegradable and polymerizable polyester composition comprises an inorganic filler in a certain content and satisfies a certain range of viscosity, it has excellent dispersibility during polycondensation; thus, it is possible to control the content of metals in a biodegradable polyester resin prepared from the biodegradable polyester polymerization composition and the dispersion index within optimal ranges. In addition, as the biodegradable and polymerizable polyester composition comprising an inorganic filler is subjected to a polycondensation reaction, the dispersibility during the polycondensation reaction is very excellent, which can suppress the aggregation of inorganic filler particles and prevent filter clogging, resulting in a decrease in defects such as voids in the processing process.

Abstract: An electronic device includes a semiconductor memory including material layers each including one or more low-resistance areas and one or more high-resistance areas, insulating layers stacked alternately with the material layers and including protrusions extending more than the material layers, conductive pillars passing through the insulating layers and the low-resistance areas, conductive layers located between the protrusions, and variable resistance layers interposed between the low-resistance areas and the conductive layers.

Abstract: A method of fabricating a semiconductor device includes forming a plurality of mask patterns comprising a real mask pattern and a dummy mask pattern on a substrate, removing the dummy mask pattern and etching the substrate using the real mask pattern as a mask to form a first trench, a second trench, and a fin-type pattern defined by the first trench and the second trench. The second trench contacting the fin-type pattern comprises a smooth pattern which is convex and positioned between a bottom surface and a side surface of the second trench, a first concave portion which is positioned between the side surface of the second trench and the smooth pattern, and a second concave portion which is positioned between the convex portion and the bottom surface of the second trench.

Abstract: A method of fabricating a semiconductor device includes forming a plurality of mask patterns comprising a real mask pattern and a dummy mask pattern on a substrate, removing the dummy mask pattern and etching the substrate using the real mask pattern as a mask to form a first trench, a second trench, and a fin-type pattern defined by the first trench and the second trench. The second trench contacting the fin-type pattern comprises a smooth pattern which is convex and positioned between a bottom surface and a side surface of the second trench, a first concave portion which is positioned between the side surface of the second trench and the smooth pattern, and a second concave portion which is positioned between the convex portion and the bottom surface of the second trench.

Abstract: The present invention relates to a micro power generator and power generation method using a liquid droplet to produce electricity using alternating current (AC) power induced by changing the contact areas of a liquid droplet between two electrode plates by vibration. The micro power generator according to the present invention includes first and second electrode plates positioned adjacent to and facing each other; an ion-containing liquid droplet positioned between the first and second electrode plates; and a power generation unit for producing electricity using AC voltage generated between the first and second electrode plates while as at least one of the first and second electrode plates is vibrated, a contact area between each of the first and second electrode plates and the liquid droplet changes with time.

Abstract: A semiconductor device may include lower electrodes having different heights depending on positions on a substrate. Supporting layer pattern making a contact with the lower electrodes having a relatively large height is provided. The supporting layer pattern is provided between the lower electrodes for supporting the lower electrodes. A dielectric layer is provided on the lower electrodes and the supporting layer pattern. An upper electrode is formed on the dielectric layer and has a planar upper surface. An inter-metal dielectric layer is provided on the upper electrode. A metal contact penetrating through the inter-metal dielectric layer and making a contact with the upper electrode is formed. A bottom portion of the metal contact faces a portion under where the lower electrode having a relatively small height is formed. The device has a higher reliability.

Abstract: A semiconductor device may include lower electrodes having different heights depending on positions on a substrate. Supporting layer pattern making a contact with the lower electrodes having a relatively large height is provided. The supporting layer pattern is provided between the lower electrodes for supporting the lower electrodes. A dielectric layer is provided on the lower electrodes and the supporting layer pattern. An upper electrode is formed on the dielectric layer and has a planar upper surface. An inter-metal dielectric layer is provided on the upper electrode. A metal contact penetrating through the inter-metal dielectric layer and making a contact with the upper electrode is formed. A bottom portion of the metal contact faces a portion under where the lower electrode having a relatively small height is formed. The device has a higher reliability.

Abstract: A semiconductor device may include lower electrodes having different heights depending on positions on a substrate. Supporting layer pattern making a contact with the lower electrodes having a relatively large height is provided. The supporting layer pattern is provided between the lower electrodes for supporting the lower electrodes. A dielectric layer is provided on the lower electrodes and the supporting layer pattern. An upper electrode is formed on the dielectric layer and has a planar upper surface. An inter-metal dielectric layer is provided on the upper electrode. A metal contact penetrating through the inter-metal dielectric layer and making a contact with the upper electrode is formed. A bottom portion of the metal contact faces a portion under where the lower electrode having a relatively small height is formed. The device has a higher reliability.

Abstract: In a method of estimating a self refresh period of a semiconductor memory device according to an exemplary embodiment, a plurality of internal address signals are reset in response to a refresh reset signal. The plurality of internal address signals are sequentially changed synchronously with an oscillation signal. A refresh completion signal is generated based on the plurality of internal address signals. The self refresh period is detected based on the refresh reset signal and the refresh completion signal.

Abstract: A semiconductor memory device includes a voltage level selection unit configured to output a plurality of voltage level selection signals according to a fuse program in response to a self-refresh command signal and a reference voltage generator configured to receive a reference voltage and output a target reference voltage having a different voltage level depending on a normal mode or a self-refresh mode in response to the voltage level selection signals.

Abstract: A semiconductor device may include lower electrodes having different heights depending on positions on a substrate. Supporting layer pattern making a contact with the lower electrodes having a relatively large height is provided. The supporting layer pattern is provided between the lower electrodes for supporting the lower electrodes. A dielectric layer is provided on the lower electrodes and the supporting layer pattern. An upper electrode is formed on the dielectric layer and has a planar upper surface. An inter-metal dielectric layer is provided on the upper electrode. A metal contact penetrating through the inter-metal dielectric layer and making a contact with the upper electrode is formed. A bottom portion of the metal contact faces a portion under where the lower electrode having a relatively small height is formed. The device has a higher reliability.

Abstract: A backlight assembly and a liquid crystal display device having the same backlight assembly are provided. The backlight assembly includes a bottom case, a plurality of printed circuit boards (PCBs) disposed on the bottom case, wherein substantially all of the PCBs have predetermined inclinations with respect to a front surface of the bottom case, and a plurality of light emitting diodes (LEDs) mounted on the PCBs.

Abstract: A semiconductor memory device includes a test address generating circuit configured on the device. The test address generating circuit generates a plurality of test addresses for a test of the semiconductor memory device in response to at least one externally applied test address generation signal. As a result, the number of DUTs can increase, based on a reduction of required address pins, and manufacturing productivity and test efficiency of semiconductor memory devices can increase.

Abstract: A liquid crystal display device may include a backlight unit for providing light for the display. A backlight unit may include light modules. The light modules include colored LEDs surrounded by a first lens for refracting the light from the LEDs. A second lens surrounds the first lens for further refraction of the light to improve brightness and the uniformity of the light.

Abstract: In a method of estimating a self refresh period of a semiconductor memory device according to an exemplary embodiment, a plurality of internal address signals are reset in response to a refresh reset signal. The plurality of internal address signals are sequentially changed synchronously with an oscillation signal. A refresh completion signal is generated based on the plurality of internal address signals. The self refresh period is detected based on the refresh reset signal and the refresh completion signal.

Abstract: A semiconductor memory device includes a voltage level selection unit configured to output a plurality of voltage level selection signals according to a fuse program in response to a self-refresh command signal and a reference voltage generator configured to receive a reference voltage and output a target reference voltage having a different voltage level depending on a normal mode or a self-refresh mode in response to the voltage level selection signals.

Abstract: In a layout structure of pads and a structure of pad used for a test or wire bonding of a semiconductor device, a size of at least one or more non-wire bonding pads is relatively small as compared with a size of at least one or more pads to be used for wire bonding of the semiconductor device. In the pad structure, a pad includes a wire bonding region that has an embossed surface for a portion of top metal layer within a determined pad size to improve the bonding process, and a probe tip contact region that does not have the embossed surface for a surface portion of the top metal layer within the determined pad size, so as to reduce wear of probe tip during testing of the device. Pad pitch can thereby be increased within a limited region, and peripheral circuits can be further formed in regions that would have been occupied in a conventional pad formation region. Higher integration of semiconductor devices and reduced wear of probe tip in probing is thereby realized.