Abstract: The present disclosure relates to an SNP marker set for dog identification and a dog identification method using the same. The present disclosure can accurately and easily readably identify individual dogs through the SNP markers on the gene and combinations of the SNPs based on the simple results of AA/AB/BB (Homozygote/Heterozygote/Homo mutant) by using 381 single nucleotide polymorphisms (SNPs) on the gene, thereby proving to be useful for animal individual identification.

Abstract: A multilayer electronic component includes: a body having first and second surfaces opposing each other in a first direction, and third and fourth surfaces connected to first and second surfaces and opposing each other in a second direction; a first external electrode including a first connection portion disposed on the third surface, a first band portion extending from the first connection portion onto a portion of the first surface, and a third band portion extending from the first connection portion onto a portion of the second surface; a second external electrode including a second connection portion disposed on the fourth surface, and a second band portion extending from the second connection portion onto a portion of the first surface; an insulating layer including a silicone-based resin and disposed on the first and second connection portions.

Abstract: A multilayer electronic component includes a body including a dielectric layer and first and second internal electrodes alternately disposed with the dielectric layer interposed therebetween and including first and second surfaces opposing each other in a first direction, third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other in a third direction.

Abstract: An electronic component includes a body including a dielectric layer and internal electrodes, and including first to sixth surfaces; a first external electrode including a first connection portion on the third surface and a first band portion on the first surface; a second external electrode including a second connection portion on the fourth surface and a second band portion on the first surface; an insulating layer on the second surface and the first and second connection portions; and a plating layer on the first and second band portions. The plating layer extends onto the first and second connection portions and is in contact with the insulating layer. A thickness of an end of the insulating layer decreases toward the plating layer. An end of the plating layer includes a first region between the insulating layer and the first or second connection portion and a second region covering the insulating layer.

Abstract: A multilayer capacitor includes: a body including a capacitance region in which at least one first internal electrode and at least one second internal electrode are alternately laminated in a first direction with at least one dielectric layer interposed therebetween; and first and second external electrodes spaced apart from each other and respectively disposed on first and second surfaces of the body, the first and second surfaces opposing each other. The body further includes a first via electrode, connecting the at least one first internal electrode and the first external electrode to each other in the first direction, and a second via electrode connecting the at least one second internal electrode and the second external electrode to each other in the first direction.

Abstract: A semiconductor device includes a first active pattern on a substrate. The first active pattern includes a pair of first source/drain patterns and a first channel pattern therebetween. A gate electrode is disposed on the first channel pattern, and a first gate spacer is disposed on a side surface of the gate electrode. The first gate spacer includes a first spacer and a second spacer. A top surface of the first spacer is lower than a top surface of the second spacer. A first blocking pattern is disposed on the first spacer, and a gate contact is coupled to the gate electrode. The first blocking pattern is interposed between the gate contact and the second spacer.

Abstract: A semiconductor device includes a first active pattern on a substrate. The first active pattern includes a pair of first source/drain patterns and a first channel pattern therebetween. A gate electrode is disposed on the first channel pattern, and a first gate spacer is disposed on a side surface of the gate electrode. The first gate spacer includes a first spacer and a second spacer. A top surface of the first spacer is lower than a top surface of the second spacer. A first blocking pattern is disposed on the first spacer, and a gate contact is coupled to the gate electrode. The first blocking pattern is interposed between the gate contact and the second spacer.

Abstract: A semiconductor device includes a first active pattern on a substrate. The first active pattern includes a pair of first source/drain patterns and a first channel pattern therebetween. A gate electrode is disposed on the first channel pattern, and a first gate spacer is disposed on a side surface of the gate electrode. The first gate spacer includes a first spacer and a second spacer. A top surface of the first spacer is lower than a top surface of the second spacer. A first blocking pattern is disposed on the first spacer, and a gate contact is coupled to the gate electrode. The first blocking pattern is interposed between the gate contact and the second spacer.

Abstract: A semiconductor device includes a source/drain region in a fin-type active pattern, a gate structure adjacent to the source/drain region, and an insulating layer on the source/drain region and the gate structure. A shared contact plug penetrates through the insulating layer and includes a first lower portion connected to the source/drain region, a second lower portion connected to the gate structure, and an upper portion connected to upper surfaces of the first lower portion and the second lower portion. A plug spacer film is between the insulating layer and at least one of the first lower portion and the second lower portion and includes a material different from a material of the insulating layer.

Abstract: A method for automatically generating blank-space inference questions for a foreign language sentence, according to the present invention, comprises the steps of: receiving one or more foreign language sentence; designating a range to be set as blank spaces among the inputted foreign language sentences; designating setting information for generating a wrong-answer sheet; and generating blank-space inference questions according to the blank range and the setting information by using a sentence generation algorithm based on preset artificial intelligence.

Abstract: A semiconductor device includes a first active pattern on a substrate. The first active pattern includes a pair of first source/drain patterns and a first channel pattern therebetween. A gate electrode is disposed on the first channel pattern, and a first gate spacer is disposed on a side surface of the gate electrode. The first gate spacer includes a first spacer and a second spacer. A top surface of the first spacer is lower than a top surface of the second spacer. A first blocking pattern is disposed on the first spacer, and a gate contact is coupled to the gate electrode. The first blocking pattern is interposed between the gate contact and the second spacer.

Abstract: A semiconductor device includes a source/drain region in a fin-type active pattern, a gate structure adjacent to the source/drain region, and an insulating layer on the source/drain region and the gate structure. A shared contact plug penetrates through the insulating layer and includes a first lower portion connected to the source/drain region, a second lower portion connected to the gate structure, and an upper portion connected to upper surfaces of the first lower portion and the second lower portion. A plug spacer film is between the insulating layer and at least one of the first lower portion and the second lower portion and includes a material different from a material of the insulating layer.

Abstract: A semiconductor device includes a source/drain region in a fin-type active pattern, a gate structure adjacent to the source/drain region, and an insulating layer on the source/drain region and the gate structure. A shared contact plug penetrates through the insulating layer and includes a first lower portion connected to the source/drain region, a second lower portion connected to the gate structure, and an upper portion connected to upper surfaces of the first lower portion and the second lower portion. A plug spacer film is between the insulating layer and at least one of the first lower portion and the second lower portion and includes a material different from a material of the insulating layer.

Abstract: Disclosed is a semiconductor device including a first active pattern and a second active pattern that extend in a first direction on a substrate and are spaced apart from each other in a second direction crossing the first direction, a first gate structure that extends across the first and second active patterns, a second gate structure that is spaced apart from the first gate structure, and a node contact between the first and second gate structures that electrically connects the first active pattern and the second active pattern to each other. The node contact comprises a first end adjacent to the first active pattern and a second end adjacent to the second active pattern. The second end of the node contact being shifted in the first direction relative to the first end of the node contact so as to be closer to the second gate structure than to the first gate structure.

Abstract: The present invention relates to a photocurable resin composition usable in a nanoimprint process which is capable of overcoming low productivity of conventional semiconductor processes for optical devices and electronic devices, and a method of forming patterns using the same. Specifically, the present invention relates to a photocurable resin composition including a specific perfluorinated acrylic compound for improving release property between a nanoimprint mold and the photocurable resin composition, and a method of forming patterns using the same.

Abstract: The present invention relates to an adhesive composition capable of improving adhesion force between two interfaces through thermal crosslinking and photo-crosslinking of a substrate and a resin, or a resin and a resin, in processes for optical devices and electronic devices, and a preparation method thereof. Specifically, the present invention relates to an adhesive composition capable of adhering an interface between a substrate and a photocurable resin, and a method of adhering an interface using the same.

Abstract: Bioconjugation methods for promoting wound healing are disclosed. In particular, the invention relates to the in situ application of non-photochemical crosslinking techniques such as copper-free click chemistry using strain-promoted azide-alkyne cycloaddition (SPAAC) or multi-functional succinimidyl esters as a therapeutic delivery modality for biomolecules and stem cells to enhance wound healing.

Abstract: A semiconductor device includes a substrate including active patterns, a device isolation layer filling a trench between a pair of adjacent active patterns, a gate electrode on the active patterns, and a gate contact on the gate electrode. Each active pattern includes source/drain patterns at opposite sides of the gate electrode. The gate contact includes a first portion vertically overlapping with the gate electrode, and a second portion laterally extending from the first portion such that the second portion vertically overlaps with the device isolation layer and does not vertically overlap with the gate electrode. A bottom surface of the second portion is distal to the substrate in relation to a bottom surface of the first portion. The bottom surface of the second portion is distal to the substrate in relation to a top of a source/drain pattern that is adjacent to the second portion.

Abstract: A semiconductor device includes a lower interlayer insulating film including a first trench and a second trench adjacent each other; a first gate structure within the first trench and extending in a first direction; a second gate structure within the second trench and extending in the first direction; a source/drain adjacent the first gate structure and the second gate structure; an upper interlayer insulating film on the lower interlayer insulating film; and a contact connected to the source/drain, the contact in the upper interlayer insulating film and the lower interlayer insulating film, wherein the contact includes a first side wall and a second side wall, the first side wall of the contact and the second side wall of the contact are asymmetric with each other, and the contact does not vertically overlap the first gate structure and the second gate structure.

Abstract: A semiconductor device includes a source/drain region in a fin-type active pattern, a gate structure adjacent to the source/drain region, and an insulating layer on the source/drain region and the gate structure. A shared contact plug penetrates through the insulating layer and includes a first lower portion connected to the source/drain region, a second lower portion connected to the gate structure, and an upper portion connected to upper surfaces of the first lower portion and the second lower portion. A plug spacer film is between the insulating layer and at least one of the first lower portion and the second lower portion and includes a material different from a material of the insulating layer.