Abstract: Magnetic devices, and methods of manufacturing the same, include a stack structure including at least one magnetic layer, etched using an etching gas including at least 70 volume percent of a hydrogen-containing gas and at least 2 volume percent of CO gas.

Abstract: In a method of manufacturing an MRAM device, a first sacrificial layer, an etch stop layer, and a second sacrificial layer are sequentially formed on a substrate and then partially etched to form openings therethrough. Lower electrodes are formed to fill the openings. The first and second sacrificial layers and portions of the etch stop layer are removed to form etch stop layer patterns surrounding upper portions of sidewalls of the lower electrodes, respectively. An upper insulating layer pattern is formed between the etch stop layer patterns to partially define an air pad between the lower electrodes. A first magnetic layer, a tunnel barrier layer, a second magnetic layer, and an upper electrode layer are formed, and are etched to form a plurality of magnetic tunnel junction (MTJ) structures.

Abstract: In a method of an MRAM device, first and second patterns are formed on a substrate alternately and repeatedly in a second direction. Each first pattern and each second pattern extend in a first direction perpendicular to the second direction. Some of the second patterns are removed to form first openings extending in the first direction. Source lines filling the first openings are formed. A mask is formed on the first and second patterns and the source lines. The mask includes second openings in the first direction, each of which extends in the second direction. Portions of the second patterns exposed by the second openings are removed to form third openings. Third patterns filling the third openings are formed. The second patterns surrounded by the first and third patterns are removed to form fourth openings. Contact plugs filling the fourth openings are formed.

Abstract: In a method of manufacturing an MRAM device, a first sacrificial layer, an etch stop layer, and a second sacrificial layer are sequentially formed on a substrate and then partially etched to form openings therethrough. Lower electrodes are formed to fill the openings. The first and second sacrificial layers and portions of the etch stop layer are removed to form etch stop layer patterns surrounding upper portions of sidewalls of the lower electrodes, respectively. An upper insulating layer pattern is formed between the etch stop layer patterns to partially define an air pad between the lower electrodes. A first magnetic layer, a tunnel barrier layer, a second magnetic layer, and an upper electrode layer are formed, and are etched to form a plurality of magnetic tunnel junction (MTJ) structures.

Abstract: A method of manufacturing a magnetic device includes forming a stack structure, the stack structure including a magnetic layer, and etching the stack structure by using an etching gas, the etching gas including at least 80% by volume of H2 gas.

Abstract: In a method of an MRAM device, first and second patterns are formed on a substrate alternately and repeatedly in a second direction. Each first pattern and each second pattern extend in a first direction perpendicular to the second direction. Some of the second patterns are removed to form first openings extending in the first direction. Source lines filling the first openings are formed. A mask is formed on the first and second patterns and the source lines. The mask includes second openings in the first direction, each of which extends in the second direction. Portions of the second patterns exposed by the second openings are removed to form third openings. Third patterns filling the third openings are formed. The second patterns surrounded by the first and third patterns are removed to form fourth openings. Contact plugs filling the fourth openings are formed.

Abstract: A magnetic body structure including: a magnetic layer pattern; and a conductive pattern including a metallic glass alloy and covering at least a portion of the magnetic body structure.

Abstract: A magnetic body structure including: a magnetic layer pattern; and a conductive pattern including a metallic glass alloy and covering at least a portion of the magnetic body structure.

Abstract: Magnetic devices, and methods of manufacturing the same, include a stack structure including at least one magnetic layer, etched using an etching gas including at least 70 volume percent of a hydrogen-containing gas and at least 2 volume percent of CO gas.

Abstract: A method of manufacturing a magnetic device includes forming a stack structure, the stack structure including a magnetic layer, and etching the stack structure by using an etching gas, the etching gas including at least 80% by volume of H2 gas.

Abstract: Methods for manufacturing a magnetic tunnel junction structure include forming a magnetic tunnel junction (MTJ) layer by sequentially stacking a first ferromagnetic layer, a tunnel insulation layer, and a second ferromagnetic layer on a substrate, forming a mask pattern on the MTJ layer, and etching at least a portion of the MTJ layer in an etching chamber using the mask pattern as an etch mask, wherein the etching of the at least a portion of the MTJ layer includes applying a RF source power to a first electrode of the etching chamber as first RF power in a first pulselike mode, and applying a RF bias power to a second electrode of the etching chamber as second RF power in a second pulselike mode. The second pulselike mode of the RF bias power has a different phase from the first pulselike mode of the RF source power.

Abstract: A random access memory (RAM) device for use in a high-speed pipelined Reed-Solomon decoder, a method of accessing the memory device, and a Reed-Solomon decoder having the memory device are provided. The memory device, which data is written to and read from at the same time during decoding of one frame of data, includes a random access memory (RAM) having a plurality of banks; and a control circuit for setting a first bank pointer, which selects a first bank among the plurality of banks, and a second bank pointer which selects a second bank among the plurality of banks, wherein the first and second bank pointers are set to banks with a predetermined offset every frame of data.

Abstract: There is provided a method of forming a semiconductor device. According to the method, a gate pattern having a capping insulating layer is formed on a substrate, a first etch stop layer is conformably formed. A first interlayer insulating layer having a planarized upper surface, a second etch stop layer and a second interlayer insulating layer are sequentially formed on the first etch stop layer. A first opening and a second opening are formed. The first opening penetrates the second interlayer insulating layer, the second etch stop layer, the first interlayer insulating layer, the first etch stop layer and the capping insulating pattern to expose the gate electrode, and the second opening penetrates the second interlayer insulating layer, the second etch stop layer, the first interlayer insulating layer and the first etch stop layer to expose the substrate. The forming the first and second openings includes at least one selective etching process and a nonselective etching process.

Abstract: A method and system for error correcting C1/PI words using error locations detected by EFM/EFM+ decoder are provided. The method for channel decoding and error correcting includes: (a) setting up a channel code; (b) producing demodulated data including information data symbols and erasure flags by modulating channel data symbols, using the channel code; and (c) performing an error-erasure correction on the information data symbols of the demodulated data, using error locations indicated by the erasure flags. The system for channel decoding and error correcting includes a channel decoder with a channel code for producing the demodulated data having the information data symbols and the erasure flags by demodulating the channel data symbols, a memory for storing the demodulated data, and a decoding unit for performing an error-erasure correction on the information data symbols, using the error locations indicated by the erasure flags having a predetermined value.

Abstract: A pattern buffer apparatus for a dynamic write strategy, which buffers non return to zero (NRZ) data patterns in order to generate a recording pulse in a compact disc system, includes a pattern detector which detects a pattern edge and a pattern from the NRZ data; a write address generating unit which generates a write address indicating a pattern buffer which stores the pattern in response to a write enable signal; the pattern buffer which has a plurality of registers and stores the detected pattern according to the write address; and a read address generating unit which generates a read address in response to a read enable signal, and reads the current pattern stored in the pattern buffer indicated by the read address.

Abstract: A random access memory (RAM) device for use in a high-speed pipelined Reed-Solomon decoder, a method of accessing the memory device, and a Reed-Solomon decoder having the memory device are provided. The memory device, which data is written to and read from at the same time during decoding of one frame of data, includes a random access memory (RAM) having a plurality of banks; and a control circuit for setting a first bank pointer, which selects a first bank among the plurality of banks, and a second bank pointer which selects a second bank among the plurality of banks, wherein the first and second bank pointers are set to banks with a predetermined offset every frame of data.

Abstract: A random access memory (RAM) device for use in a high-speed pipelined Reed-Solomon decoder, a method of accessing the memory device, and a Reed-Solomon decoder having the memory device are provided. The memory device, which data is written to and read from at the same time during decoding of one frame of data, includes a random access memory (RAM) having a plurality of banks; and a control circuit for setting a first bank pointer, which selects a first bank among the plurality of banks, and a second bank pointer which selects a second bank among the plurality of banks, wherein the first and second bank pointers are set to banks with a predetermined offset every frame of data.

Abstract: A method and system for error correcting C1/PI words using error locations detected by EFM/EFM+ decoder are provided. The method for channel decoding and error correcting includes: (a) setting up a channel code; (b) producing demodulated data including information data symbols and erasure flags by modulating channel data symbols, using the channel code; and (c) performing an error-erasure correction on the information data symbols of the demodulated data, using error locations indicated by the erasure flags. The system for channel decoding and error correcting includes a channel decoder with a channel code for producing the demodulated data having the information data symbols and the erasure flags by demodulating the channel data symbols, a memory for storing the demodulated data, and a decoding unit for performing an error-erasure correction on the information data symbols, using the error locations indicated by the erasure flags having a predetermined value.

Abstract: A memory device employs multiple dual-bank RAMs to allow simultaneous write/read operations. The memory may be utilized in a high-speed block pipelined Reed-Solomon decoder for temporarily storing input codewords during pipelined processing. A memory controller enables writing to and reading from the dual-bank RAMs during each of successive frame periods such that each bank of the dual-bank RAMs is read every given number of frame periods and is written every same given number of frame periods, and such that a read bank is contained in a different one of the dual-bank RAMs than is a write bank in each of the successive frame periods.

Abstract: A link method and system for providing recorded data continuity in a compact disc. When a buffer underrun occurs, the width of an EXTENDED SYNC signal indicating the time interval between an absolute time in pre-groove synchronization (ATIP SYNC) signal and a SUBCODE SYNC signal is stored in a predetermined place, and is then used for accurate data recording continuity when data recording restarts after the buffer underrun is corrected.