Abstract: Computer implemented methods of designing integrated circuits and computing systems are provided. A computer implemented method of designing an integrated circuit according to the inventive concepts may be performed by a processor and may include performing a placement and routing (P&R) operation for standard cells defining the integrated circuit, extracting characteristic values from a result of the P&R operation, generating a physical-aware annotation file by determining a plurality of representative characteristic values that respectively correspond to a plurality of groups based on the extracted characteristic values, and performing a physical-aware synthesis operation to generate a netlist from input data for the integrated circuit, based on the generated physical-aware annotation file.

Abstract: A method of generating an integrated circuit design includes receiving input data defining input cells of the integrated circuit design, selecting first standard cells from a first standard cell library to represent the input cells having a first characteristic, selecting second standard cells from a second standard cell library to represent the input cells having a second characteristic different from the first characteristic, and generating output data representing the integrated circuit design by performing placement and routing on the selected first standard cells and the selected second standard cells. The first standard cell library includes a first type of standard cells manufactured using a first diffusion break scheme. The second standard cell library includes a second type of standard cells manufactured using a second diffusion break scheme. Each of the second type of standard cells has a same function as a respective one of the first type of standard cells.

Abstract: A system and method of designing an integrated circuit (IC) by considering a local layout effect are provided. The method of designing an IC may place instances of pre-placement cells so as to decrease occurrence of a local layout effect (LLE) causing structure. The method may extract a context of an instance from a peripheral layout of each of the placed instances to estimate an LLE of the instance, thereby analyzing a performance of the IC.

Abstract: A method of generating an integrated circuit design includes receiving input data defining input cells of the integrated circuit design, selecting first standard cells from a first standard cell library to represent the input cells having a first characteristic, selecting second standard cells from a second standard cell library to represent the input cells having a second characteristic different from the first characteristic, and generating output data representing the integrated circuit design by performing placement and routing on the selected first standard cells and the selected second standard cells. The first standard cell library includes a first type of standard cells manufactured using a first diffusion break scheme. The second standard cell library includes a second type of standard cells manufactured using a second diffusion break scheme. Each of the second type of standard cells has a same function as a respective one of the first type of standard cells.

Abstract: A method of manufacturing an integrated circuit (IC) including instances of standard cells includes arranging a first instance and arranging a second instance adjacent to the first instance. The second instance has a front-end layer pattern corresponding to a context group of the first instance. The context group includes information about front-end layer patterns of instances, the front-end layer patterns causing a same local layout effect (LLE) on the first instance and arranged adjacent to the first instance.

Abstract: A method of manufacturing an integrated circuit may include placing cells, based on input data defining the integrated circuit, performing a pin reordering operation on a plurality of pins in a first cell of the cells, based on physical information regarding the pins in the first cell, wherein the physical information is determined based on the placement of the cells, performing a routing operation on the cells after the pin reordering operation, and manufacturing the integrated circuit, based on a layout produced by the routing operation.

Abstract: Computer implemented methods of designing integrated circuits and computing systems are provided. A computer implemented method of designing an integrated circuit according to the inventive concepts may be performed by a processor and may include performing a placement and routing (P&R) operation for standard cells defining the integrated circuit, extracting characteristic values from a result of the P&R operation, generating a physical-aware annotation file by determining a plurality of representative characteristic values that respectively correspond to a plurality of groups based on the extracted characteristic values, and performing a physical-aware synthesis operation to generate a netlist from input data for the integrated circuit, based on the generated physical-aware annotation file.

Abstract: A method of manufacturing an integrated circuit (IC) including instances of standard cells includes arranging a first instance and arranging a second instance adjacent to the first instance. The second instance has a front-end layer pattern corresponding to a context group of the first instance. The context group includes information about front-end layer patterns of instances, the front-end layer patterns causing a same local layout effect (LLE) on the first instance and arranged adjacent to the first instance.

Abstract: A system-on-chip and an electronic device including the system-on-chip are provided. The system-on-chip includes a power switch, a logic block, a memory device, and a buffer. The power switch is coupled between a first power supply line and a virtual power supply line, and turns on in response to a switch control signal. The logic block is coupled between the virtual power supply line and a ground line. The memory device is coupled between a second power supply line and the ground line. The buffer is coupled between the second power supply line and the ground line, and generates the switch control signal based on a sleep signal.

Abstract: A method for placing a parallel multiplier with a placement and routing tool includes receiving a datapath netlist about the parallel multiplier, extracting locations of primary input cells and primary output cells from the datapath netlist using a structure analysis module, mapping the primary input cells and the primary output cells on a specific array using the placement and routing tool, and arranging columns of the primary input cells and the primary output cells based on physical sizes of the primary input cells. The columns are arranged using the placement and routing tool. The size of the specific array is determined according to a number of the primary input cells.

Abstract: A method of manufacturing an integrated circuit may include placing cells, based on input data defining the integrated circuit, performing a pin reordering operation on a plurality of pins in a first cell of the cells, based on physical information regarding the pins in the first cell, wherein the physical information is determined based on the placement of the cells, performing a routing operation on the cells after the pin reordering operation, and manufacturing the integrated circuit, based on a layout produced by the routing operation.

Abstract: A system and method of designing an integrated circuit (IC) by considering a local layout effect are provided. The method of designing an IC may place instances of pre-placement cells so as to decrease occurrence of a local layout effect (LLE) causing structure. The method may extract a context of an instance from a peripheral layout of each of the placed instances to estimate an LLE of the instance, thereby analyzing a performance of the IC.

Abstract: A system-on-chip and an electronic device including the system-on-chip are provided. The system-on-chip includes a power switch, a logic block, a memory device, and a buffer. The power switch is coupled between a first power supply line and a virtual power supply line, and turns on in response to a switch control signal. The logic block is coupled between the virtual power supply line and a ground line. The memory device is coupled between a second power supply line and the ground line. The buffer is coupled between the second power supply line and the ground line, and generates the switch control signal based on a sleep signal.

Abstract: A method for placing a parallel multiplier with a placement and routing tool includes receiving a datapath netlist about the parallel multiplier, extracting locations of primary input cells and primary output cells from the datapath netlist using a structure analysis module, mapping the primary input cells and the primary output cells on a specific array using the placement and routing tool, and arranging columns of the primary input cells and the primary output cells based on physical sizes of the primary input cells. The columns are arranged using the placement and routing tool. The size of the specific array is determined according to a number of the primary input cells.

Abstract: A power control circuit is connected between a power supply voltage and a logic circuit to switch power supplied to the logic circuit. The power control circuit includes a plurality of first power gating cells (PGCs) receiving an external mode change signal in parallel, at least one second PGC connected with one first PGC, at least one third PGC connected with the at least one second PGC, and at least one fourth PGC connected with the at least one third PGC. The second power gating cell, the third PGC, and/or the fourth PGC may include a plurality of gating cells. At least one of the second, third, and fourth pluralities has power gating cells connected in series. Each of the first through fourth PGCs switches power supplied in response to the mode change signal.

Abstract: In a method of designing a system-on-chip including a tapless standard cell to which body biasing is applied, a slow corner timing parameter is adjusted to increase a slow corner of an operating speed distribution for the system-on-chip by reflecting forward body biasing, and a fast corner timing parameter is adjusted to decrease a fast corner of the operating speed distribution for the system-on-chip by reflecting reverse body biasing. The system-on-chip including the tapless standard cell is implemented based on the adjusted slow corner timing parameter corresponding to the increased slow corner and the adjusted fast corner timing parameter corresponding to the decreased fast corner. The slow corner timing parameter corresponds to a lowest value of an operating speed design window of the system-on-chip, and, the fast corner timing parameter corresponds to a highest value of the operating speed design window of the system-on-chip.

Abstract: In a method of designing a system-on-chip including a tapless standard cell to which body biasing is applied, a slow corner timing parameter is adjusted to increase a slow corner of an operating speed distribution for the system-on-chip by reflecting forward body biasing, and a fast corner timing parameter is adjusted to decrease a fast corner of the operating speed distribution for the system-on-chip by reflecting reverse body biasing. The system-on-chip including the tapless standard cell is implemented based on the adjusted slow corner timing parameter corresponding to the increased slow corner and the adjusted fast corner timing parameter corresponding to the decreased fast corner. The slow corner timing parameter corresponds to a lowest value of an operating speed design window of the system-on-chip, and, the fast corner timing parameter corresponds to a highest value of the operating speed design window of the system-on-chip.

Abstract: A method of constructing a standard cell library for double patterning lithography (DPL) includes dividing a standard cell into a first region determined not to have an interaction with an adjacent outer cell and a second region that is likely to have such an interaction, generating data representative of DPL patterns corresponding to the first and second regions, and generating a standard cell library made up of the data. The library is then accessed and used to form a DPL mask. The DPL mask can be used to form a pattern on a substrate made up of a layout of cells in which the pattern of the standard cell is duplicated at several locations in the layout.

Abstract: A power control circuit is connected between a power supply voltage and a logic circuit to switch power supplied to the logic circuit. The power control circuit includes a plurality of first power gating cells (PGCs) receiving an external mode change signal in parallel, at least one second PGC connected with one first PGC, at least one third PGC connected with the at least one second PGC, and at least one fourth PGC connected with the at least one third PGC. The second power gating cell, the third PGC, and/or the fourth PGC may include a plurality of gating cells. At least one of the second, third, and fourth pluralities has power gating cells connected in series. Each of the first through fourth PGCs switches power supplied in response to the mode change signal.

Abstract: A method of controlling the provision of a body bias voltage to a logic gate region of a semiconductor device includes; gating application of a clock signal applied to a synchronization element in the logic gate region in accordance with an enable signal, and providing the body bias voltage to each body terminal of a plurality of logic gates arranged in the logic gate region in accordance with the enable signal.