Abstract: Proposed is an impeller-type exhaust apparatus for blocking transfer of heat including a first disc facing a high-temperature gas, a second disc spaced apart from the first disc to form a heat blocking space, a plurality of blades formed along the circumferences of the first disc and the second disc, and a motor which provides rotary power to the first disc and the second disc, wherein heat can be blocked through the heat blocking space.

Abstract: Proposed is an impeller-type exhaust apparatus for blocking transfer of heat including a first disc facing a high-temperature gas, a second disc spaced apart from the first disc to form a heat blocking space, a plurality of blades formed along the circumferences of the first disc and the second disc, and a motor which provides rotary power to the first disc and the second disc, wherein heat can be blocked through the heat blocking space.

Abstract: The present invention provides a molten-salt electrolytic refining apparatus for refining a raw-material alloy containing indium using a molten-salt electrolytic refining method. The molten-salt electrolytic refining apparatus includes a reaction crucible provided in a reaction container so as to be filled with a molten-salt electrolytic solution, an anode and a cathode immersed in the molten-salt electrolytic solution, an anode crucible in which a liquid raw-material alloy is contained, a cathode crucible in which at least one raw-material metal included in the raw-material alloy is recovered in a liquid phase, and a heater provided so that the temperature of the molten-salt electrolytic solution is adjusted to be equal to or greater than the melting temperature of the raw-material alloy. The present invention also provides a molten-salt electrolytic refining method which includes recovering indium (In) from an indium-tin (In—Sn) alloy using a molten-salt electrolytic solution containing fluoride.

Abstract: Disclosed is a memory device including a multi-bit perpendicular magnetic tunnel junction, wherein the multi-bit perpendicular magnetic tunnel junction includes an upper synthetic antiferromagnetic layer, pinned layer, lower dual free layer, and upper free layer formed in a laminated manner between a top electrode and a bottom electrode.

Abstract: Disclosed is a memory device including a multi-bit perpendicular magnetic tunnel junction, wherein the multi-bit perpendicular magnetic tunnel junction includes an upper synthetic antiferromagnetic layer, pinned layer, lower dual free layer, and upper free layer formed in a laminated manner between a top electrode and a bottom electrode.

Abstract: Provided is a method of diagnosing cervical cancer using an artificial intelligence-based medical image analysis, which is performed by a computer, the method including obtaining an image of cervical cells of an object; pre-processing the image; identifying one or more cells in the pre-processed image; determining whether the identified one or more cells are normal; and diagnosing whether the object has cervical cancer on the basis of a result of determining whether the identified one or more cells are normal.

Abstract: The present invention provides a molten-salt electrolytic refining apparatus for refining a raw-material alloy containing indium using a molten-salt electrolytic refining method. The molten-salt electrolytic refining apparatus includes a reaction crucible provided in a reaction container so as to be filled with a molten-salt electrolytic solution, an anode and a cathode immersed in the molten-salt electrolytic solution, an anode crucible in which a liquid raw-material alloy is contained, a cathode crucible in which at least one raw-material metal included in the raw-material alloy is recovered in a liquid phase, and a heater provided so that the temperature of the molten-salt electrolytic solution is adjusted to be equal to or greater than the melting temperature of the raw-material alloy. The present invention also provides a molten-salt electrolytic refining method which includes recovering indium (In) from an indium-tin (In—Sn) alloy using a molten-salt electrolytic solution containing fluoride.

Abstract: Provided are an operation method for a camera operation apparatus, the method including the steps of: obtaining a bio-signal of a user from a wearable sensor; determining, based on the bio-signal, whether a state of a user is a stable state; setting the camera to a low power mode if the state of the user is a stable state; determining the type of bio-signal if the state of the user is not a stable state; and setting the camera to a mode in accordance with the type of the bio-signal.

Abstract: Provided are an operation method for a camera operation apparatus, the method including the steps of: obtaining a bio-signal of a user from a wearable sensor; determining, based on the bio-signal, whether a state of a user is a stable state; setting the camera to a low power mode if the state of the user is a stable state; determining the type of bio-signal if the state of the user is not a stable state; and setting the camera to a mode in accordance with the type of the bio-signal.

Abstract: An image processing apparatus and a method thereof are provided. The image processing apparatus includes at least one processor configured to implement: a decoder which decodes input image data; and a rendering module which renders the decoded image data according to a rendering cycle which corresponds to a refresh rate of a display to display a plurality of image frames of the image data, wherein the decoder decodes the input image data only when the processor is not being in use for rendering by the rendering module.

Abstract: A compound represented by Chemical Formula 1, an organic optoelectronic device including the same, and a display device including the organic optoelectronic device are provided. The structure of the compound represented by Chemical Formula 1 is described in the present specification.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs a command and a mask command. The second semiconductor device drives a first local line according to data on a first global line if a first mask write operation is performed in response to the command and the mask command. In addition, the second semiconductor device senses and amplifies data on a second local line if the first mask write operation is performed in response to the command and the mask command.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs a command and a mask command. The second semiconductor device drives a first local line according to data on a first global line if a first mask write operation is performed in response to the command and the mask command. In addition, the second semiconductor device senses and amplifies data on a second local line if the first mask write operation is performed in response to the command and the mask command.

Abstract: A memory device including first to fourth cell blocks, each including a plurality of normal columns and one or more redundancy columns and a control unit suitable for repairing the normal columns using the redundancy columns in the first and the second cell blocks using first repair information and repairing the normal columns using the redundancy columns in the third and the fourth cell blocks using second repair information when the memory device is set as a first mode, and suitable for repairing the normal columns using the redundancy columns in the first and the third cell blocks using the first repair information and repairing the normal columns using the redundancy columns in the second and the fourth cell blocks using the second repair information when the memory device is set as a second mode.

Abstract: An image processing apparatus and a method thereof are provided. The image processing apparatus includes at least one processor configured to implement: a decoder which decodes input image data; and a rendering module which renders the decoded image data according to a rendering cycle which corresponds to a refresh rate of a display to display a plurality of image frames of the image data, wherein the decoder decodes the input image data only when the processor is not being in use for rendering by the rendering module.

Abstract: A memory device including first to fourth cell blocks, each including a plurality of normal columns and one or more redundancy columns and a control unit suitable for repairing the normal columns using the redundancy columns in the first and the second cell blocks using first repair information and repairing the normal columns using the redundancy columns in the third and the fourth cell blocks using second repair information when the memory device is set as a first mode, and suitable for repairing the normal columns using the redundancy columns in the first and the third cell blocks using the first repair information and repairing the normal columns using the redundancy columns in the second and the fourth cell blocks using the second repair information when the memory device is set as a second mode.

Abstract: A compound represented by Chemical Formula 1, an organic optoelectronic device including the same, and a display device including the organic optoelectronic device are provided. The structure of the compound represented by Chemical Formula 1 is described in the present specification.

Abstract: A latch circuit may include first to fourth storage nodes; first to fourth transistor pairs, each including a PMOS transistor and an NMOS transistor connected in series through a corresponding one of the first to fourth storage nodes, wherein each of the first to fourth storage nodes is connected to a gate of an NMOS transistor of a transistor pair in a previous stage and a gate of a PMOS transistor of a transistor pair in a next stage; a first connection unit suitable for connecting a data bus with a Kth storage node of the first to fourth storage nodes when read and write operations are performed, wherein K is an integer from 1 to 4; and second connection units suitable for connecting the data bus with one or more of the first to fourth storage nodes, except for the Kth storage node, when the write operation is performed.

Abstract: A latch circuit may include first to fourth storage nodes; first to fourth transistor pairs, each including a PMOS transistor and an NMOS transistor connected in series through a corresponding one of the first to fourth storage nodes, wherein each of the first to fourth storage nodes is connected to a gate of an NMOS transistor of a transistor pair in a previous stage and a gate of a PMOS transistor of a transistor pair in a next stage; a first connection unit suitable for connecting a data bus with a Kth storage node of the first to fourth storage nodes when read and write operations are performed, wherein K is an integer from 1 to 4; and second connection units suitable for connecting the data bus with one or more of the first to fourth storage nodes, except for the Kth storage node, when the write operation is performed.

Abstract: A compound for an organic optoelectronic device, an organic light-emitting device including the same, and a display device including the organic light-emitting device are disclosed, the compound for an organic optoelectronic device being represented by Chemical Formula 1,