Abstract: Disclosed is a non-volatile memory device including a first memory plane circuit, a second memory plane circuit, a first page buffer circuit connected to the first memory plane circuit, a second page buffer circuit connected to the second memory plane circuit, and a control logic circuit. During a first sequence, the control logic circuit provides first latch control signals to the first page buffer circuit to receive first verification information and provides second latch control signals to the second page buffer circuit to receive second verification information. During a second sequence following the first sequence, the control logic circuit enables the first page buffer circuit to perform a second program operation based on the first verification information indicating a pass state and enables the second page buffer circuit to perform the first program operation based on the second verification information indicating a fail state.

Abstract: The present disclosure relates to a method of operating a memory device including a plurality of memory blocks, each memory block of the plurality of memory blocks including a plurality of pages. An example method includes receiving a read command and an address for controlling a read operation, identifying whether a selected memory block among the plurality of memory blocks is an open block, the selected memory block corresponding to the address, and based on the selected memory block being identified as the open block, controlling a read pass voltage applied to at least one of unselected pages among a plurality of pages included in the selected memory block, the at least one unselected page being different from a selected page corresponding to the address.

Abstract: a non-volatile memory device comprising a memory cell array including a first physical page and a second physical page, wherein the first physical page includes first memory cells connected to the first word line and the second physical page includes second memory cells connected to the first word line, a row decoder configured to sequentially perform a first program operation on the first memory cells of the first physical page and perform a second program operation on the second memory cells of the second physical page, a page buffer circuit configured to perform an accumulation operation on first and second data for generating a accumulated data, and to perform a verify operation on the first and second memory cells based on the accumulated data, and a control logic configured to determine whether the first and second memory cells passed the program operations based on the result of the verify operation.

Abstract: A battery assembly machine includes a gripper configured to be movable and to double grip a cell block in which a plurality of cells is stacked, and a pusher configured to provide pressing force for inserting the cell block gripped by the gripper into a case.

Abstract: The present disclosure provides a laser protection system including a laser source configured to sequentially radiate a laser beam to two or more work targets that are discretely supplied, a plurality of protective lenses disposed between the laser source and the work targets, the plurality of protective lenses each allowing the laser beam to pass therethrough at different times, and a drive mechanism having the plurality of protective lenses movably mounted thereon.

Abstract: In accordance with an embodiment, a battery assembly device includes a holder unit configured to hold a structure and to transfer the structure to a target to be mounted, an alignment jig operatively associated with the holder unit, and configured to align the target, and a transfer unit configured to provide a moving force to the alignment jig.

Abstract: A battery module includes: a battery cell stack including a plurality of battery cells stacked on each other in a first direction; a pair of cell covers which is in surface contact with both side surfaces of the battery cell stack; a housing which covers side surfaces of the pair of cell covers in the first direction and top surfaces of the battery cell stack. In particular, a bottom side of the housing is open.

Abstract: A nonvolatile memory device includes a memory cell region including first metal pads and a memory cell array, and a peripheral circuit region including second metal pads, row decoder circuitry that is connected to the rows of the memory cells through word lines and controls voltages of the word lines, and page buffer circuitry that is connected to the columns of the memory cells through bit lines. The page buffer circuitry is configured to obtain first values by performing a first sensing operation on first bit lines of the bit lines through the first transistors and obtain second values by performing a second sensing operation on the second bit lines of the bit lines through the second transistors, wherein the first values or the second values are inverted. The peripheral circuit region is vertically connected to the memory cell region by the metal pads directly.

Abstract: A nonvolatile memory device includes a memory cell array that includes memory cells arranged in rows and columns, row decoder circuitry that is connected to the rows of the memory cells through word lines and controls voltages of the word lines, and page buffer circuitry that is connected to the columns of the memory cells through bit lines and includes first transistors configured to sense voltages of the bit lines and second transistors configured to invert and sense the voltages of the bit lines. The page buffer circuitry is configured to obtain first values by performing a first sensing operation on first bit lines of the bit lines through the first transistors and obtain second values by performing a second sensing operation on the second bit lines of the bit lines through the second transistors, wherein the first values or the second values are inverted.

Abstract: A nonvolatile memory device may include a page buffer including a plurality of latch sets that latch each page datum of selected memory cells among a plurality of memory cells according to each of read signal sets including at least one read signal, and a control logic configured to detect a degradation level of the memory cells and determine a read parameter applied to at least one of the read signal sets based on the detected degradation level.

Abstract: A nonvolatile memory device includes a memory cell region including first metal pads and a memory cell array, and a peripheral circuit region including second metal pads, row decoder circuitry that is connected to the rows of the memory cells through word lines and controls voltages of the word lines, and page buffer circuitry that is connected to the columns of the memory cells through bit lines. The page buffer circuitry is configured to obtain first values by performing a first sensing operation on first bit lines of the bit lines through the first transistors and obtain second values by performing a second sensing operation on the second bit lines of the bit lines through the second transistors, wherein the first values or the second values are inverted. The peripheral circuit region is vertically connected to the memory cell region by the metal pads directly.

Abstract: A nonvolatile memory device includes a memory cell array that includes memory cells arranged in rows and columns, row decoder circuitry that is connected to the rows of the memory cells through word lines and controls voltages of the word lines, and page buffer circuitry that is connected to the columns of the memory cells through bit lines and includes first transistors configured to sense voltages of the bit lines and second transistors configured to invert and sense the voltages of the bit lines. The page buffer circuitry is configured to obtain first values by performing a first sensing operation on first bit lines of the bit lines through the first transistors and obtain second values by performing a second sensing operation on the second bit lines of the bit lines through the second transistors, wherein the first values or the second values are inverted.

Abstract: A nonvolatile memory device may include a page buffer including a plurality of latch sets that latch each page datum of selected memory cells among a plurality of memory cells according to each of read signal sets including at least one read signal, and a control logic configured to detect a degradation level of the memory cells and determine a read parameter applied to at least one of the read signal sets based on the detected degradation level.

Abstract: A nonvolatile memory device may include a page buffer including a plurality of latch sets that latch each page datum of selected memory cells among a plurality of memory cells according to each of read signal sets including at least one read signal, and a control logic configured to detect a degradation level of the memory cells and determine a read parameter applied to at least one of the read signal sets based on the detected degradation level.

Abstract: A nonvolatile memory device may include a page buffer including a plurality of latch sets that latch each page datum of selected memory cells among a plurality of memory cells according to each of read signal sets including at least one read signal, and a control logic configured to detect a degradation level of the memory cells and determine a read parameter applied to at least one of the read signal sets based on the detected degradation level.

Abstract: A nonvolatile memory device includes a memory cell array including a plurality of memory cells, an address decoder configured to be connected to the memory cells through a plurality of word lines and to provide select or unselect read voltages to the word lines, and a control logic configured to control the address decoder to perform a plurality of read sequences in a continuous read mode and to adjust a word line setup start point in at least one of the read sequences to be different than a word line setup start point in at least one of the other read sequences, wherein the word line setup start point is a time at which the select or unselect read voltages begin to be provided to the word lines.

Abstract: A store terminal including a reception module configured to receive an order from an order relay system, the order relay system being configured to take the order requested by a user terminal and relay the order to the store terminal, and an output module configured to output the order externally.

Abstract: A nonvolatile memory device includes a memory cell array including a plurality of memory cells, an address decoder configured to be connected to the memory cells through a plurality of word lines and to provide select or unselect read voltages to the word lines, and a control logic configured to control the address decoder to perform a plurality of read sequences in a continuous read mode and to adjust a word line setup start point in at least one of the read sequences to be different than a word line setup start point in at least one of the other read sequences, wherein the word line setup start point is a time at which the select or unselect read voltages begin to be provided to the word lines.

Abstract: A nonvolatile memory device includes a cell array including a plurality of cell strings extending on a substrate in a vertical direction, a page buffer connected to a plurality of bit lines and configured to store sensing data of the cell array in a sensing operation, a voltage generator configured to provide voltages to a plurality of word lines and the plurality of bit lines, and an input/output buffer configured to temporarily store the sensing data received in a data dump from the page buffer and to output the temporarily stored data to an external device. The nonvolatile memory device further includes control logic configured to set a status of the nonvolatile memory device to a ready state after the sensing data is dumped to the input/output buffer and before recovery of the cell array from a bias voltage of the sensing operation is complete.

Abstract: A nonvolatile memory device includes a cell array including a plurality of cell strings extending on a substrate in a vertical direction, a page buffer connected to a plurality of bit lines and configured to store sensing data of the cell array in a sensing operation, a voltage generator configured to provide voltages to a plurality of word lines and the plurality of bit lines, and an input/output buffer configured to temporarily store the sensing data received in a data dump from the page buffer and to output the temporarily stored data to an external device. The nonvolatile memory device further includes control logic configured to set a status of the nonvolatile memory device to a ready state after the sensing data is dumped to the input/output buffer and before recovery of the cell array from a bias voltage of the sensing operation is complete.