Patents by Inventor Hyun Kwang Shin

Hyun Kwang Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11869129
    Abstract: A learning apparatus for image generation includes a preprocessing module configured to receive text for image generation and generate a sentence feature vector and a word feature vector from the received text, a first generative adversarial network (GAN) configured to receive the sentence feature vector from the preprocessing module and generate an initial image based on the received sentence feature vector, and a second generative adversarial network configured to receive the word feature vector generated by the preprocessing module and the initial image generated by the first generative adversarial network and generate a final image based on the word feature vector and the initial image.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: January 9, 2024
    Assignee: RESEARCH COOPERATION FOUNDATION OF YEUNGNAM UNIVERSITY
    Inventors: Gyu Sang Choi, Jong Ho Han, Hyun Kwang Shin
  • Publication number: 20230378172
    Abstract: A semiconductor device includes a ring-shaped gate electrode having an opening area disposed on a substrate, a source region and a bulk tap region disposed in the opening area, a well region disposed to overlap the ring-shaped gate electrode, a drift region disposed to be in contact with the well region, a first insulating isolation region disposed, on the drift region, to partially overlap the gate electrode, a second insulating isolation region enclosing the bulk tap region, a drain region disposed to be spaced apart from the ring-shaped gate electrode, and a deep trench isolation region disposed adjacent to the drain region.
    Type: Application
    Filed: August 7, 2023
    Publication date: November 23, 2023
    Applicant: Key Foundry Co., Ltd.
    Inventor: Hyun Kwang SHIN
  • Patent number: 11764216
    Abstract: A semiconductor device includes a ring-shaped gate electrode having an opening area disposed on a substrate, a source region and a bulk tap region disposed in the opening area, a well region disposed to overlap the ring-shaped gate electrode, a drift region disposed to be in contact with the well region, a first insulating isolation region disposed, on the drift region, to partially overlap the gate electrode, a second insulating isolation region enclosing the bulk tap region, a drain region disposed to be spaced apart from the ring-shaped gate electrode, and a deep trench isolation region disposed adjacent to the drain region.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: September 19, 2023
    Assignee: KEY FOUNDRY CO., LTD.
    Inventor: Hyun Kwang Shin
  • Publication number: 20230274479
    Abstract: A learning apparatus for image generation includes a preprocessing module configured to receive text for image generation and generate a sentence feature vector and a word feature vector from the received text, a first generative adversarial network (GAN) configured to receive the sentence feature vector from the preprocessing module and generate an initial image based on the received sentence feature vector, and a second generative adversarial network configured to receive the word feature vector generated by the preprocessing module and the initial image generated by the first generative adversarial network and generate a final image based on the word feature vector and the initial image.
    Type: Application
    Filed: September 29, 2021
    Publication date: August 31, 2023
    Inventors: Gyu Sang CHOI, Jong Ho HAN, Hyun Kwang SHIN
  • Patent number: 11688795
    Abstract: A semiconductor device is disclosed. A semiconductor device according to an example of the present disclosure includes a gate electrode of a ring shape having an opening area on a substrate; a P-type deep well region formed in the opening area; a drain region formed on the P-type deep well region; an N-type well region overlapping with the gate electrode; a source region formed in the N-type well region; a bulk tab region formed by being isolated from the source region by a first isolation region; a P-type drift region formed in contact with the N-type well region; and a second isolation region formed near the bulk tab region.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: June 27, 2023
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Hyun Kwang Shin, Jung Hwan Lee
  • Patent number: 11568647
    Abstract: A learning apparatus for creating an emotion expression video according to an embodiment disclosed include first generative adversarial networks (GAN) that receive text for creating an emotion expression video, extract vector information by performing embedding on the input text, and create an image based on the extracted vector information, and second generative adversarial networks that receive an emotion expression image and a frame of comparison video, and create a frame of emotion expression video from the emotion expression image and the frame of comparison video.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: January 31, 2023
    Assignee: RESEARCH COOPERATION FOUNDATION OF YEUNGNAM UNIVERSITY
    Inventors: Gyu Sang Choi, Jong Ho Han, Hyun Kwang Shin
  • Publication number: 20230005152
    Abstract: An apparatus for image segmentation according to an embodiment includes an acquirer configured to acquire one or more images in which an object is photographed and a segmentation performer configured to perform segmentation on the one or more images using a segmentation model which is deep learned through a plurality of images, in which the segmentation model is a U-Net-based model including a first type module based on depth-wise separable convolution (DSC) and a second type module based on global context network (GCNet).
    Type: Application
    Filed: April 19, 2022
    Publication date: January 5, 2023
    Inventors: Gyu Sang CHOI, Hyun Kwang SHIN
  • Patent number: 11532741
    Abstract: A semiconductor device includes a substrate, a buried doped layer formed on the substrate, a trench gate formed on the buried doped layer, a source region formed adjacent the trench gate, an interlayer dielectric layer formed on the trench gate and the source region, a source contact plug formed to extend and connect to the source region, and a drain contact plug, extending and connecting to the buried doped layer, formed deeper than the source contact plug.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: December 20, 2022
    Assignee: KEY FOUNDRY CO., LTD.
    Inventor: Hyun Kwang Shin
  • Publication number: 20220302303
    Abstract: A trench power MOSFET includes a body region disposed on a semiconductor substrate, a trench passing through the body region, an top electrode and a bottom electrode spaced apart from each other in a vertical direction in the trench, an inter-electrode dielectric layer disposed between the top electrode and the bottom electrode, and a plurality of dielectric layers, disposed between a sidewall of the trench and the bottom electrode, comprising a first oxide layer disposed on the sidewall of the trench, an barrier layer disposed on the first oxide layer, and a second oxide layer disposed on the barrier layer. The barrier layer is formed of a material different from materials of the first and second oxide layers.
    Type: Application
    Filed: November 4, 2021
    Publication date: September 22, 2022
    Applicant: KEY FOUNDRY CO., LTD.
    Inventor: Hyun Kwang SHIN
  • Publication number: 20220262927
    Abstract: A semiconductor device is disclosed. A semiconductor device according to an example of the present disclosure includes a gate electrode of a ring shape having an opening area on a substrate; a P-type deep well region formed in the opening area; a drain region formed on the P-type deep well region; an N-type well region overlapping with the gate electrode; a source region formed in the N-type well region; a bulk tab region formed by being isolated from the source region by a first isolation region; a P-type drift region formed in contact with the N-type well region; and a second isolation region formed near the bulk tab region.
    Type: Application
    Filed: May 3, 2022
    Publication date: August 18, 2022
    Applicant: KEY FOUNDRY CO., LTD.
    Inventors: Hyun Kwang SHIN, Jung Hwan LEE
  • Publication number: 20220189955
    Abstract: A semiconductor device includes a ring-shaped gate electrode having an opening area disposed on a substrate, a source region and a bulk tap region disposed in the opening area, a well region disposed to overlap the ring-shaped gate electrode, a drift region disposed to be in contact with the well region, a first insulating isolation region disposed, on the drift region, to partially overlap the gate electrode, a second insulating isolation region enclosing the bulk tap region, a drain region disposed to be spaced apart from the ring-shaped gate electrode, and a deep trench isolation region disposed adjacent to the drain region.
    Type: Application
    Filed: March 8, 2022
    Publication date: June 16, 2022
    Applicant: KEY FOUNDRY CO., LTD.
    Inventor: Hyun Kwang SHIN
  • Patent number: 11362197
    Abstract: A semiconductor device is disclosed. A semiconductor device according to an example of the present disclosure includes a gate electrode of a ring shape having an opening area on a substrate; a P-type deep well region formed in the opening area; a drain region formed on the P-type deep well region; an N-type well region overlapping with the gate electrode; a source region formed in the N-type well region; a bulk tab region formed by being isolated from the source region by a first isolation region; a P-type drift region formed in contact with the N-type well region; and a second isolation region formed near the bulk tab region.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: June 14, 2022
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Hyun Kwang Shin, Jung Hwan Lee
  • Patent number: 11322492
    Abstract: A semiconductor device includes a ring-shaped gate electrode having an opening area disposed on a substrate, a source region and a bulk tap region disposed in the opening area, a well region disposed to overlap the ring-shaped gate electrode, a drift region disposed to be in contact with the well region, a first insulating isolation region disposed, on the drift region, to partially overlap the gate electrode, a second insulating isolation region enclosing the bulk tap region, a drain region disposed to be spaced apart from the ring-shaped gate electrode, and a deep trench isolation region disposed adjacent to the drain region.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: May 3, 2022
    Assignee: KEY FOUNDRY CO., LTD.
    Inventor: Hyun Kwang Shin
  • Publication number: 20220059689
    Abstract: A semiconductor device includes a substrate, a buried doped layer formed on the substrate, a trench gate formed on the buried doped layer, a source region formed adjacent the trench gate, an interlayer dielectric layer formed on the trench gate and the source region, a source contact plug formed to extend and connect to the source region, and a drain contact plug, extending and connecting to the buried doped layer, formed deeper than the source contact plug.
    Type: Application
    Filed: January 15, 2021
    Publication date: February 24, 2022
    Applicant: KEY FOUNDRY CO., LTD.
    Inventor: Hyun Kwang SHIN
  • Publication number: 20210406554
    Abstract: A learning apparatus for creating an emotion expression video according to an embodiment disclosed include first generative adversarial networks (GAN) that receive text for creating an emotion expression video, extract vector information by performing embedding on the input text, and create an image based on the extracted vector information, and second generative adversarial networks that receive an emotion expression image and a frame of comparison video, and create a frame of emotion expression video from the emotion expression image and the frame of comparison video.
    Type: Application
    Filed: October 30, 2020
    Publication date: December 30, 2021
    Inventors: Gyu Sang CHOI, Jong Ho HAN, Hyun Kwang SHIN
  • Patent number: 10923603
    Abstract: A semiconductor device includes a first N-type deep well region and a second N-type deep well region formed in a substrate, an N-type diffused well region formed between the first N-type deep well region and the second N-type deep well region, wherein a concentration of the N-type diffused well region is less than a concentration of the first N-type deep well region or the second N-type deep well region, a first P-type well region formed in the first N-type deep well region, a second P-type well region formed in the N-type diffused well region, an insulating film formed to be in contact with the first P-type well region, and a silicide formed on the N-type diffused well region, such that a Schottky barrier diode is formed between the silicide and the N-type diffused well.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: February 16, 2021
    Assignee: Key Foundry Co., Ltd.
    Inventors: Yon Sup Pang, Hyun Kwang Shin, Tae Hoon Lee
  • Publication number: 20210028298
    Abstract: A semiconductor device is disclosed. A semiconductor device according to an example of the present disclosure includes a gate electrode of a ring shape having an opening area on a substrate; a P-type deep well region formed in the opening area; a drain region formed on the P-type deep well region; an N-type well region overlapping with the gate electrode; a source region formed in the N-type well region; a bulk tab region formed by being isolated from the source region by a first isolation region; a P-type drift region formed in contact with the N-type well region; and a second isolation region formed near the bulk tab region.
    Type: Application
    Filed: January 21, 2020
    Publication date: January 28, 2021
    Applicant: KEY FOUNDRY CO., LTD.
    Inventors: Hyun Kwang SHIN, Jung Hwan LEE
  • Publication number: 20210028166
    Abstract: A semiconductor device includes a ring-shaped gate electrode having an opening area disposed on a substrate, a source region and a bulk tap region disposed in the opening area, a well region disposed to overlap the ring-shaped gate electrode, a drift region disposed to be in contact with the well region, a first insulating isolation region disposed, on the drift region, to partially overlap the gate electrode, a second insulating isolation region enclosing the bulk tap region, a drain region disposed to be spaced apart from the ring-shaped gate electrode, and a deep trench isolation region disposed adjacent to the drain region.
    Type: Application
    Filed: November 13, 2019
    Publication date: January 28, 2021
    Applicant: KEY FOUNDRY CO., LTD.
    Inventor: Hyun Kwang SHIN
  • Publication number: 20200105947
    Abstract: A semiconductor device includes a first N-type deep well region and a second N-type deep well region formed in a substrate, an N-type diffused well region formed between the first N-type deep well region and the second N-type deep well region, wherein a concentration of the N-type diffused well region is less than a concentration of the first N-type deep well region or the second N-type deep well region, a first P-type well region formed in the first N-type deep well region, a second P-type well region formed in the N-type diffused well region, an insulating film formed to be in contact with the first P-type well region, and a silicide formed on the N-type diffused well region, such that a Schottky barrier diode is formed between the silicide and the N-type diffused well.
    Type: Application
    Filed: December 4, 2019
    Publication date: April 2, 2020
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Yon Sup PANG, Hyun Kwang SHIN, Tae Hoon LEE
  • Patent number: 10566465
    Abstract: A semiconductor device includes a first N-type deep well region and a second N-type deep well region formed in a substrate, an N-type diffused well region formed between the first N-type deep well region and the second N-type deep well region, wherein a concentration of the N-type diffused well region is less than a concentration of the first N-type deep well region or the second N-type deep well region, a first P-type well region formed in the first N-type deep well region, a second P-type well region formed in the N-type diffused well region, an insulating film formed to be in contact with the first P-type well region, and a silicide formed on the N-type diffused well region, such that a Schottky barrier diode is formed between the silicide and the N-type diffused well.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: February 18, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Yon Sup Pang, Hyun Kwang Shin, Tae Hoon Lee