Patents by Inventor HyunWook Park

HyunWook Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020009230
    Abstract: A template is analyzed to determine a step size for searching within a search area. First, the template is padded with pixels to increase its size. Cross-correlation between the padded template and the original template leads to identification of an effective step size. Step sizes for each of horizontal and vertical axes are derived. Windows of the search area, selected based on the step size, then are tested in a fast search stage by correlating the template to the window. Any tested window which has a correlation coefficient exceeding a specific value is a local match. A full search of the vicinity of the local match then is performed for all potential windows within an area bounded by one step to either side of the local match along either axis. The location(s) corresponding to the highest correlation(s) exceeding the threshold value are matches.
    Type: Application
    Filed: August 23, 2001
    Publication date: January 24, 2002
    Inventors: Shijun Sun, HyunWook Park, Yongmin Kim
  • Patent number: 5467459
    Abstract: The present invention provides a unified image and graphics processing system that provides both image and graphics processing at high speeds. The system includes a parallel vector processing unit, a graphics subsystem, a shared memory and a set of high-speed data buses for connecting all of the other components. Generally, the parallel vector processing unit includes a series of vector processors. Each processor includes a vector address generator for efficient generation of memory addresses for regular address sequences. In order to synchronize and control the vector processors' accesses to shared memory, the parallel vector processing unit includes shared memory access logic. The logic is incorporated into each vector processor. The graphics subsystem includes a series of polygon processors in a pipelined configuration. Each processor is connected in the pipeline by a first-in-first-out (FIFO) buffer for passing data results.
    Type: Grant
    Filed: August 2, 1993
    Date of Patent: November 14, 1995
    Assignees: Board of Regents of the University of Washington, Samsung Electronics
    Inventors: Thomas Alexander, Yongmin Kim, Hyunwook Park, Kil-Su Eo, Jing-Ming Jong