Patents by Inventor I-Min Lu
I-Min Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190187520Abstract: A backlight module for an LCD display includes backlight units. Each backlight unit includes a backplane unit, a first reflecting unit on the backplane unit, an LED on the backplane unit extending through the first reflecting unit, and a light guiding unit on a side of the LED and the first reflecting unit away from the backplane unit. The light guiding unit is transparent. Each backlight unit further includes a second reflecting unit on a side of the light guiding unit away from the backplane unit. The second reflecting unit includes at least one reflecting region and at least one transmitting region. The reflecting region reflects light; the transmitting region allows light to pass through. At least one backlight unit comprises a quantum dot layer.Type: ApplicationFiled: December 20, 2018Publication date: June 20, 2019Inventors: WEI-CHIH CHANG, I-MIN LU, KUAN-HSIEN JIANG
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Patent number: 10281772Abstract: An LCD device includes a TFT array substrate, a liquid crystal layer, and a plurality of photo spacers. The photo spacers are located inside the liquid crystal layer. The TFT array substrate includes a pixel electrode layer and an alignment layer. The alignment layer is arranged on the of TFT array substrate on the side near the liquid crystal layer. The pixel electrode layer is arranged on the alignment layer on the side far away from liquid crystal layer; the alignment layer includes a plurality of contact portion. The bottom of the photo spacers are holding with the contact portions. A plurality of block portion is adjacent to the contact portions. The block portion is a protrusion formed toward the color filter substrate with respect to the contact portion, so that the displacement of the photo spacers on the TFT array substrate can be limited.Type: GrantFiled: October 25, 2017Date of Patent: May 7, 2019Assignee: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: I-Wei Chen, Hsin-An Cheng, Wun-Zong Chang, Hao-Ting Tien, I-Min Lu
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Publication number: 20190027506Abstract: A conductive layer for a thin film transistor (TFT) array panel includes a multi-layered portion defining a source electrode and a drain electrode of a TFT device, and includes a first sub-layer, a second sub-layer, a third sub-layer, and at least one additional sub-layer. The third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. An indium to zinc content ratio in the additional sub-layer is formulated between that in the first and the third sub-layers. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that in the first sub-layer.Type: ApplicationFiled: December 13, 2016Publication date: January 24, 2019Inventors: PO-LI SHIH, YI-CHUN KAO, HSIN-HUA LIN, CHIH-LUNG LEE, WEI-CHIH CHANG, I-MIN LU
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Publication number: 20190019870Abstract: A thin film transistor array panel includes a first conductive layer (102) including a gate electrode; a channel layer (104) disposed over the gate; and a second conductive layer (105) disposed over the channel layer (104). The second conductive layer (105) includes a multi-layered portion defining a source electrode (105a) and a drain electrode (105b), which includes a first sub-layer (105-1), a second sub-layer (105-2), and a third sub-layer (105-3) sequentially disposed one over another. Both the third and the first sub-layers (105-3, 105-1) include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer (105-1) is greater than that in the third sub-layer (105-3).Type: ApplicationFiled: December 7, 2016Publication date: January 17, 2019Applicants: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.Inventors: YI-CHUN KAO, HSIN-HUA LIN, PO-LI SHIH, WEI-CHIH CHANG, I-MIN LU, I-WEI WU
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Publication number: 20180113339Abstract: An LCD device includes a TFT array substrate, a liquid crystal layer, and a plurality of photo spacers. The photo spacers are located inside the liquid crystal layer. The TFT array substrate includes a pixel electrode layer and an alignment layer. The alignment layer is arranged on the of TFT array substrate on the side near the liquid crystal layer. The pixel electrode layer is arranged on the alignment layer on the side far away from liquid crystal layer; the alignment layer includes a plurality of contact portion. The bottom of the photo spacers are holding with the contact portions. A plurality of block portion is adjacent to the contact portions. The block portion is a protrusion formed toward the color filter substrate with respect to the contact portion, so that the displacement of the photo spacers on the TFT array substrate can be limited.Type: ApplicationFiled: October 25, 2017Publication date: April 26, 2018Inventors: I-WEI CHEN, HSIN-AN CHENG, WUN-ZONG CHANG, HAO-TING TIEN, I-MIN LU
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Patent number: 9793409Abstract: A semiconductor device comprises a multi-layered structure disposed over a substrate and defining a composite lateral etch profile. The multi-layered structure includes a lower sub-layer disposed over the substrate and comprising a metal oxide material that includes indium and zinc, the indium and zinc content in the bottom sub-layer substantially defining a first indium to zinc content ratio; a middle sub-layer disposed over the bottom sub-layer and comprising a metal material; an upper sub-layer disposed over the middle sub-layer and comprising a metal oxide material that includes indium and zinc, the indium to zinc content in the upper sub-layer substantially defining a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and a lateral byproduct layer formed over the lateral etched surface, comprising substantially an metal oxide of the metal material in the middle sub-layer.Type: GrantFiled: March 31, 2016Date of Patent: October 17, 2017Assignee: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Yi-Chun Kao, Hsin-Hua Lin, Po-Li Shih, Wei-Chih Chang, I-Min Lu, I-Wei Wu
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Patent number: 9728650Abstract: A thin film transistor array panel includes a first conductive layer including a gate electrode; a channel layer disposed over the gate; and a second conductive layer disposed over the channel layer. The second conductive layer includes a multi-layered portion defining a source electrode and a drain electrode, which includes a first sub-layer, a second sub-layer, and a third sub-layer sequentially disposed one over another. Both the third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that that in the first sub-layer.Type: GrantFiled: March 15, 2016Date of Patent: August 8, 2017Assignee: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Yi-Chun Kao, Hsin-Hua Lin, Po-Li Shih, Wei-Chih Chang, I-Min Lu, I-Wei Wu
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Publication number: 20170207243Abstract: A semiconductor device comprises a multi-layered structure disposed over a substrate and defining a composite lateral etch profile. The multi-layered structure includes a lower sub-layer disposed over the substrate and comprising a metal oxide material that includes indium and zinc, the indium and zinc content in the bottom sub-layer substantially defining a first indium to zinc content ratio; a middle sub-layer disposed over the bottom sub-layer and comprising a metal material; an upper sub-layer disposed over the middle sub-layer and comprising a metal oxide material that includes indium and zinc, the indium to zinc content in the upper sub-layer substantially defining a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and a lateral byproduct layer formed over the lateral etched surface, comprising substantially an metal oxide of the metal material in the middle sub-layer.Type: ApplicationFiled: March 31, 2016Publication date: July 20, 2017Inventors: YI-CHUN KAO, HSIN-HUA LIN, PO-LI SHIH, WEI-CHIH CHANG, I-MIN LU, I-WEI WU
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Publication number: 20170207342Abstract: A thin film transistor array panel includes a first conductive layer including a gate electrode; a channel layer disposed over the gate; and a second conductive layer disposed over the channel layer. The second conductive layer includes a multi-layered portion defining a source electrode and a drain electrode, which includes a first sub-layer, a second sub-layer, and a third sub-layer sequentially disposed one over another. Both the third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that that in the first sub-layer.Type: ApplicationFiled: March 15, 2016Publication date: July 20, 2017Inventors: YI-CHUN KAO, HSIN-HUA LIN, PO-LI SHIH, WEI-CHIH CHANG, I-MIN LU, I-WEI WU
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Patent number: 9576984Abstract: A conductive layer for a thin film transistor (TFT) array panel includes a multi-layered portion defining a source electrode and a drain electrode of a TFT device, and includes a first sub-layer, a second sub-layer, a third sub-layer, and at least one additional sub-layer. The third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. An indium to zinc content ratio in the additional sub-layer is formulated between that in the first and the third sub-layers. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that that in the first sub-layer.Type: GrantFiled: March 15, 2016Date of Patent: February 21, 2017Assignee: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Po-Li Shih, Yi-Chun Kao, Hsin-Hua Lin, Chih-Lung Lee, Wei-Chih Chang, I-Min Lu
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Patent number: 9478669Abstract: A thin film transistor includes a gate electrode, a gate insulating layer, a channel layer, an etching stop layer, two contact holes, a source, and a drain. The gate insulating layer covers the gate electrode. The channel layer is arranged on the gate insulating layer corresponding to the gate electrode. The etching stop layer covers the channel layer and includes an organic stop layer and a hard mask layer, the hard mask layer is located on a surface of the organic stop layer opposite to the channel layer to enhance a hardness of the organic stop layer. The two contact holes pass through the etching stop layer. The source connects to the channel via one contact hole, and the drain connects to the channel via the other contact hole.Type: GrantFiled: August 25, 2014Date of Patent: October 25, 2016Assignee: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: I-Wei Wu, I-Min Lu, Wei-Chih Chang, Hui-Chu Lin, Yi-Chun Kao, Kuo-Lung Fang
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Patent number: 8980704Abstract: A manufacturing method of a thin film transistor includes hard-baking and etching processes for a stop layer. Two through holes are exposed and developed in a photoresistor layer, in which a distance between the two through holes is substantially equal to the channel length of the thin film transistor. Further, the etching stop layer is dry-etched to obtain the thin film transistor having an expected channel length.Type: GrantFiled: August 25, 2014Date of Patent: March 17, 2015Assignee: Ye Xin Technology Consulting Co., Ltd.Inventors: I-Wei Wu, I-Min Lu, Wei-Chih Chang, Hui-Chu Lin, Yi-Chun Kao, Kuo-Lung Fang
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Publication number: 20150056761Abstract: A manufacturing method of a thin film transistor includes hard-baking and etching processes for a stop layer. Two through holes are exposed and developed in a photoresistor layer, in which a distance between the two through holes is substantially equal to the channel length of the thin film transistor. Further, the etching stop layer is dry-etched to obtain the thin film transistor having an expected channel length.Type: ApplicationFiled: August 25, 2014Publication date: February 26, 2015Inventors: I-WEI WU, I-MIN LU, WEI-CHIH CHANG, HUI-CHU LIN, YI-CHUN KAO, KUO-LUNG FANG
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Publication number: 20150053974Abstract: A thin film transistor includes a gate electrode, a gate insulating layer, a channel layer, an etching stop layer, two contact holes, a source, and a drain. The gate insulating layer covers the gate electrode. The channel layer is arranged on the gate insulating layer corresponding to the gate electrode. The etching stop layer covers the channel layer and includes an organic stop layer and a hard mask layer, the hard mask layer is located on a surface of the organic stop layer opposite to the channel layer to enhance a hardness of the organic stop layer. The two contact holes pass through the etching stop layer. The source connects to the channel via one contact hole, and the drain connects to the channel via the other contact hole.Type: ApplicationFiled: August 25, 2014Publication date: February 26, 2015Inventors: I-WEI WU, I-MIN LU, WEI-CHIH CHANG, HUI-CHU LIN, YI-CHUN KAO, KUO-LUNG FANG
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Publication number: 20100201713Abstract: The present invention discloses an image display apparatus and a method thereof. The image display apparatus having an output picture includes a receiver module and an operation module. The receiver module receives at least one image having a display proportion. The operation module splits the output picture to generate a plurality of display areas according to the display proportion, wherein the image is displayed in the plurality of display areas.Type: ApplicationFiled: August 26, 2009Publication date: August 12, 2010Applicant: MATRIXVIXION TECHNOLOGY Inc.Inventor: I-Min Lu
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Patent number: 7112458Abstract: An active layer of a P-type low temperature polysilicon thin film transistor and a bottom electrode of a storage capacitor are first formed. Then, a P-type source/drain is formed and the bottom electrode is doped with dopants. A gate insulator, a gate electrode, a capacitor dielectric, and a top electrode are thereafter formed. Finally, a source interconnect, a drain interconnect, and a pixel electrode of the liquid crystal display are formed.Type: GrantFiled: October 2, 2003Date of Patent: September 26, 2006Assignee: TPO Displays Corp.Inventors: Chu-Jung Shih, Gwo-Long Lin, I-Min Lu
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Patent number: 6924874Abstract: The present invention provides a method of forming a liquid crystal display (LCD). Active layers of N-type and P-type low temperature polysilicon thin film transistors and a bottom electrode of a storage capacitor are formed first. Then a N-type source/drain is formed and the bottom electrode is doped with dopants. A gate insulator, a gate electrode, a capacitor dielectric, and a top electrode are thereafter formed. After that, a P-type source/drain is formed. Finally, a source interconnect, a drain interconnect, and a pixel electrode of the liquid crystal display are formed.Type: GrantFiled: June 5, 2003Date of Patent: August 2, 2005Assignee: Toppoly Optoelectronics Corp.Inventors: Gwo-Long Lin, I-Min Lu, Chu-Jung Shih, Shyuan-Jeng Ho, I-Wei Wu
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Publication number: 20050072754Abstract: An active layer of a P-type low temperature polysilicon thin film transistor and a bottom electrode of a storage capacitor are first formed. Then, a P-type source/drain is formed and the bottom electrode is doped with dopants. A gate insulator, a gate electrode, a capacitor dielectric, and a top electrode are thereafter formed. Finally, a source interconnect, a drain interconnect, and a pixel electrode of the liquid crystal display are formed.Type: ApplicationFiled: October 2, 2003Publication date: April 7, 2005Inventors: Chu-Jung Shih, Gwo-Long Lin, I-Min Lu
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Publication number: 20040141127Abstract: A liquid crystal display (LCD) of reduced reflection phenomenon is provided. The data lines and gate lines of the LCD have an anti-reflection layer thereon. The anti-reflection layer decreases ambient light reflection. Thus, the CONTRAST of the LCD is improved.Type: ApplicationFiled: January 12, 2004Publication date: July 22, 2004Inventors: Yaw-Ming Tsai, I-Min Lu, Shih-Chang Chang
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Patent number: 6740569Abstract: A method of fabricating a polysilicon film by an excimer laser annealing process is introduced. First, an amorphous silicon film is deposited on a substrate composed of glass. The amorphous silicon film includes a first region, which is located in the center, with a first thickness, and a second region, which is located in the periphery, with a slant sidewall. The thickness of the amorphous silicon film is measured so as to obtain the profile of the sidewall in the second region. According to the profile of the sidewall, a pre-cursor region is determined for performing an excimer laser annealing process wherein a second thickness in the boundary of the pre-curser regionis smaller than the first thickness so as to increase area of produced polysilicon film.Type: GrantFiled: January 14, 2003Date of Patent: May 25, 2004Assignee: Toppoly Optoelectronics Corp.Inventors: Chu-Jung Shih, I-Min Lu