Abstract: This is an enhanced thermoelectric cooler with superconductive heat-dissipatve coolers for use in air-conditioner. This invention is comprised of a thermoelectric cooling chip sandwiched between two superconductive unidirectional heat-dissipative cooling devices. Each device consists of special superconductive pipes, heat-dissipative plates, and a fan. The cooling devices are to dissipate heat quickly from the thermoelectric cooling chip and to maintain constant hot to cold air flow.

Abstract: An earphone includes a shell, a seat, a speaker and a ring. The shell defines a sound field. The seat includes an external rim fit in the shell and an internal rim extended form the external rim. The speaker includes a terminal inserted through the internal rim. The ring is engaged with the external rim for positioning the speaker.

Abstract: A microphone includes a case, a circuit board, a plate, a cover/button element and an elastic element. The circuit board is disposed in the case and includes a transducer for receiving and converting sound waves into electric signals and a switch operable for turning on and off the circuit board. The plate is disposed in the case and defines two slots and an aperture through which the switch is exposed. A cover/button element includes at least two hooks inserted through the slots defined in the plate so that the cover/button element is movable between a normal position away from the switch of the circuit board and a pushed position in contact with the switch while always covering the case. The elastic element is sandwiched between the plate and the cover/button element for returning the cover/button element to the normal position from the pushed position.

Abstract: This is a type of superconductive vacuum heat cooler package used in computer CPU (Central Processing Unit). This invention dissipates heat through invented metal pipe materials and formula in single direction to achieve effective cooling result. This invention is to be utilized but not limited to computer Central Processing Unit.

Abstract: A method for testing signals of integrated circuits (ICs). According to the invention, a first IC chip successively drives a number of test patterns one at a time. At the receiving end, a second IC chip latches in the test patterns one by one. Meanwhile, the second IC chip determines whether a currently latched test pattern is correct or not. If it is incorrect and at least an error bit occurs, depending on the type of the test patterns, the second IC chip indicates that there exists ground bounce or power bounce in a signal trace corresponding to the error bit.

Abstract: A keyboard control apparatus with a USB interface for use in a notebook computer having a number of keys. In one embodiment, a mapping unit is employed to store a number of key matrix codes corresponding to the keys. In accordance with a clock signal and a start signal, a shift register is capable of generating a reference signal and a number of scan output signals. A key matrix circuit then receives the scan output signals to provide a number of scan input signals. An address generator is used to generate an address signal based on the reference signal and a triggered scan input signal. Thus, a selector can select one key matrix code designated to the address signal from the mapping unit. Additionally, an interface converter further converts the selected key matrix code into a pair of differential signals compliant with the USB specification.

Abstract: A signal compensation circuit of a bus is disclosed in the present invention, wherein the amplitude of a surge is obtained by inputting a test pattern into the bus and comparing a reference voltage and a peak-value signal filtered out from the bus. For continual correction of the damping resistance, the test pattern can be inputted into the bus repeatedly to optimize the effect of the compensation. Then, a proper damping resistor is selected and connected to the bus in series to absorb the energy of the surge. The signal compensation circuit is embedded in the chip, such as in the south bridge.

Abstract: Peel-off nail polish is composed of between 20% to about 30% by weight of Polyacryate, between 8% to about 18% by weight of Plasticiser, between 0.5% to about 5% by weight of Anti-setting agent, and between 60% to about 70% by weight of Solvent. The nail polish can be peeled off easily after drying without the necessity of using nail polish-remover.

Abstract: A method and a related apparatus for using a dynamic random access memory (DRAM) in substitution of a hard disk drive in a computer system. The computer system has a request format transformation module for transforming a hard disk request signal into a corresponding memory request signal, a memory read/write control circuit for accessing the DRAM, and a memory refresh circuit for periodically refreshing the DRAM to maintain data stored in the DRAM. When the computer system issues the hard disk request signal, the hard disk request signal is transformed into the corresponding memory request signal to access the DRAM instead of a hard disk drive. In addition, when the computer system executes an S4 or S5 state according to the specification of advanced configuration and power interface, the memory refresh circuit will repeatedly refresh the DRAM.

Abstract: A method and related apparatus for utilizing an ACPI to maintain data stored in a DRAM includes a processor, a DRAM, a south bridge chipset, and a rechargeable battery device. The south bridge chipset includes a system controller, a buffer, a memory controller, an integrated device electronics controller, and a data conversion circuit. The data conversion circuit converts a hard-disk access command transmitted from the system controller into a memory access command of the memory controller. The memory controller accesses the buffer and the DRAM by executing the memory access command. When the computer system enters a power-saving mode, a switch is turned on allowing the battery device to constantly self-refresh the DRAM for maintaining the data stored in the DRAM. When the computer system powers up, the switch is turned off and the battery device is recharged.

Abstract: An apparatus for indicating clock skew within integrated circuits (ICs) of a system. There are first and second IC chips operating on respective clocks in the system. According to the invention, the first IC chip operating on a first clock is configured to provide the first clock as output. The second IC chip operating on a second clock has a detection circuit to receive as input the first and the second clocks and to generate a compare signal as output, where the width of the compare signal is proportional to the amount of skew between the input clocks. The second IC chip also includes a sampling circuit coupled to receive the compare signal. With the sampling circuit, an output signal indicative of skew existing between the first and the second clocks can be asserted according to the compare signal.

Abstract: A primary functional circuit board with the capability to verify the chip function by an alternative manner and a simplified design for reducing the fabrication cost includes circuit board, chip, verifying apparatus, and extending connection terminals distributed on periphery of the chip. The chip is disposed on the circuit board to execute a functional instruction of the primary functional circuit board. The extending connection terminals are the extension of connection pins of the chip. The verifying apparatus is implemented with a programmable chip having a firmware program needed for controlling the circuit under control. After the verifying apparatus is connected to the extending connection terminals, the switching device is used to select the chip or the programmable chip to control the circuit under control. The engineer can easily compare the difference between the two without a power interruption.

Abstract: A timing adjustment device, method and chip for a bus interface. Through repetitive adjustment of the amount of phase shift in the clocking signal to the bus interface, read/write testing of the bus interface and checking for the correctness of the read/write data, suitability of the phase shift in the memory bus clocking signal for operating normally is determined. Hence, a safety range for the amount of phase shift in the bus interface timing signal is found and the phase shift of the bus interface timing signal is set to the mid-point of the safety range. The method may also be applied to a system bus and the timing adjustment of signals between a control chipset bus and a memory bus.

Abstract: A new apparatus for reading keyboard-commands of a portable computer comprises a shift register, a keyboard-matrix circuit, a filter, a buffer, an address generator, a mapping device, a comparator, and an output device. The shift register is for outputting a plurality of scan-input signals and a reference signal. The keyboard-matrix circuit is for outputting a scan-output signal according to the scan-input signals. The keyboard-matrix circuit includes a plurality of nodes corresponded to the keyboard buttons, respectively. The filter is for filtering the noise of the scan-output signal. The buffer is for further stabilizing the filter signal. The address generator is for reading the location of the node corresponding to the button being pressed. The mapping device is for outputting a mapping signal corresponding to the button being pressed. The comparator is for outputting a comparing signal, which represents the command corresponded to the pressed button.

Abstract: An embedded control unit is installed in a notebook computer, so as to take the place of the programmable processor in many conventional notebook computers for controlling peripheral devices. The embedded control unit includes a plurality of peripheral controllers, so as to control the peripheral devices usually used by typical notebook computers. The peripheral controllers can be directly connected to the peripheral devices, according to the specifications for different types and/or brands of notebook computers. In addition, the peripheral controllers can achieve control of the peripheral devices according to the non-adjustable internal register settings. In this way, the control of the peripheral devices can be achieved without using firmware, thereby simplifying the notebook computer development process and reducing the development cost.

Abstract: A method for testing signals of integrated circuits (ICs). According to the invention, a first IC chip successively drives a number of test patterns one at a time. At the receiving end, a second IC chip latches in the test patterns one by one. Meanwhile, the second IC chip determines whether a currently latched test pattern is correct or not. If it is incorrect and at least an error bit occurs, depending on the type of the test patterns, the second IC chip indicates that there exists ground bounce or power bounce in a signal trace corresponding to the error bit.

Abstract: A method and related apparatus for maintaining stored data in a dynamic random access memory includes a processor, a dynamic random access memory (DRAM), a south bridge chipset, and a rechargeable battery device. The south bridge chipset includes a system controller, a buffer, a memory controller, an integrated device electronics controller, and a data conversion circuit. The data conversion circuit converts a hard-disk access command transmitted from the system controller into a memory access command of the memory controller. The memory controller accesses the buffer and the DRAM by executing a memory access command. When the computer system enters a power-saving mode, a switch is turned on allowing the battery device to constantly self-refresh the DRAM for maintaining the data stored in the DRAM. When the computer system powers up, the switch is turned off and the battery device is re-charged.

Abstract: An apparatus for indicating clock skew within integrated circuits (ICs) of a system. There are first and second IC chips operating on respective clocks in the system. According to the invention, the first IC chip operating on a first clock is configured to provide the first clock as output. The second IC chip operating on a second clock has a detection circuit to receive as input the first and the second clocks and to generate a compare signal as output, where the width of the compare signal is proportional to the amount of skew between the input clocks. The second IC chip also includes a sampling circuit coupled to receive the compare signal. With the sampling circuit, an output signal indicative of skew existing between the first and the second clocks can be asserted according to the compare signal.

Abstract: A keyboard control apparatus with a USB interface for use in a notebook computer having a number of keys. In one embodiment, a mapping unit is employed to store a number of key matrix codes corresponding to the keys. In accordance with a clock signal and a start signal, a shift register is capable of generating a reference signal and a number of scan output signals. A key matrix circuit then receives the scan output signals to provide a number of scan input signals. An address generator is used to generate an address signal based on the reference signal and a triggered scan input signal. Thus, a selector can select one key matrix code designated to the address signal from the mapping unit. Additionally, an interface converter further converts the selected key matrix code into a pair of differential signals compliant with the USB specification.

Abstract: A timing adjustment device, method and chip for a bus interface. Through repetitive adjustment of the amount of phase shift in the clocking signal to the bus interface, read/write testing of the bus interface and checking for the correctness of the read/write data, suitability of the phase shift in the memory bus clocking signal for operating normally is determined. Hence, a safety range for the amount of phase shift in the bus interface timing signal is found and the phase shift of the bus interface timing signal is set to the mid-point of the safety range. The method may also be applied to a system bus and the timing adjustment of signals between a control chipset bus and a memory bus.