Patents by Inventor I-Ming Tseng

I-Ming Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11018184
    Abstract: A magnetoresistive random access memory (MRAM), including multiple cell array regions, multiple MRAM cells disposed in the cell array region, a silicon nitride liner conformally covering on the MRAM cells, an atomic layer deposition dielectric layer covering on the silicon nitride liner in the cell array region, wherein the surface of atomic layer deposition dielectric layer is a curved surface concave downward to the silicon nitride liner at the boundary of MRAM cells, and an ultra low-k dielectric layer covering on the atomic layer deposition dielectric layer.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: May 25, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Ying-Cheng Liu, Yi-Hui Lee, Chin-Yang Hsieh, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang
  • Patent number: 11005030
    Abstract: A semiconductor device preferably includes a metal-oxide semiconductor (MOS) transistor disposed on a substrate, an interlayer dielectric (ILD) layer disposed on the MOS transistor, and a magnetic tunneling junction (MTJ) disposed on the ILD layer. Preferably, a top surface of the MTJ includes a reverse V-shape while the top surface of the MTJ is also electrically connected to a source/drain region of the MOS transistor.
    Type: Grant
    Filed: March 10, 2019
    Date of Patent: May 11, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Ying-Cheng Liu, Yi-An Shih, Yi-Hui Lee, Chen-Yi Weng, Chin-Yang Hsieh, I-Ming Tseng, Jing-Yin Jhang, Yu-Ping Wang
  • Publication number: 20210111334
    Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
    Type: Application
    Filed: December 23, 2020
    Publication date: April 15, 2021
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, JUN XIE
  • Publication number: 20210035620
    Abstract: A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.
    Type: Application
    Filed: August 29, 2019
    Publication date: February 4, 2021
    Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Jing-Yin Jhang, Chien-Ting Lin
  • Patent number: 10910553
    Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: February 2, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, Jun Xie
  • Publication number: 20210020691
    Abstract: A magnetoresistive random access memory (MRAM), including multiple cell array regions, multiple MRAM cells disposed in the cell array region, a silicon nitride liner conformally covering on the MRAM cells, an atomic layer deposition dielectric layer covering on the silicon nitride liner in the cell array region, wherein the surface of atomic layer deposition dielectric layer is a curved surface concave downward to the silicon nitride liner at the boundary of MRAM cells, and an ultra low-k dielectric layer covering on the atomic layer deposition dielectric layer.
    Type: Application
    Filed: August 6, 2019
    Publication date: January 21, 2021
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Ying-Cheng Liu, Yi-Hui Lee, Chin-Yang Hsieh, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang
  • Publication number: 20210020828
    Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
    Type: Application
    Filed: August 5, 2019
    Publication date: January 21, 2021
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, JUN XIE
  • Patent number: 10892194
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate having a n-type work function metal layer or a p-type work function metal layer.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: January 12, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
  • Publication number: 20200373478
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first liner on the MTJ; forming a second liner on the first liner; forming an inter-metal dielectric (IMD) layer on the MTJ, and forming a metal interconnection in the IMD layer, the second liner, and the first liner to electrically connect the MTJ. Preferably, the first liner and the second liner are made of different materials.
    Type: Application
    Filed: June 12, 2019
    Publication date: November 26, 2020
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Publication number: 20200328126
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate having a n-type work function metal layer or a p-type work function metal layer.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 15, 2020
    Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
  • Publication number: 20200266335
    Abstract: A semiconductor device preferably includes a metal-oxide semiconductor (MOS) transistor disposed on a substrate, an interlayer dielectric (ILD) layer disposed on the MOS transistor, and a magnetic tunneling junction (MTJ) disposed on the ILD layer. Preferably, a top surface of the MTJ includes a reverse V-shape while the top surface of the MTJ is also electrically connected to a source/drain region of the MOS transistor.
    Type: Application
    Filed: March 10, 2019
    Publication date: August 20, 2020
    Inventors: Hui-Lin Wang, Ying-Cheng Liu, Yi-An Shih, Yi-Hui Lee, Chen-Yi Weng, Chin-Yang Hsieh, I-Ming Tseng, Jing-Yin Jhang, Yu-Ping Wang
  • Patent number: 10741455
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: August 11, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
  • Patent number: 10727397
    Abstract: A magneto-resistive random access memory (MRAM) cell includes a substrate having a dielectric layer disposed thereon, a conductive via disposed in the dielectric layer, and a cylindrical stack disposed on the conductive via. The cylindrical stack includes a bottom electrode, a magnetic tunneling junction (MTJ) layer on the bottom electrode, and a top electrode on the MTJ layer. A spacer layer is disposed on a sidewall of the cylindrical stack. The top electrode protrudes from a top surface of the spacer layer.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: July 28, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Yi-Wei Tseng, Meng-Jun Wang, Chen-Yi Weng, Chin-Yang Hsieh, Jing-Yin Jhang, Yu-Ping Wang, Chien-Ting Lin, Ying-Cheng Liu, Yi-An Shih, Yi-Hui Lee, I-Ming Tseng
  • Publication number: 20200227473
    Abstract: An MRAM structure includes a dielectric layer. A contact hole is disposed in the dielectric layer. A contact plug fills in the contact hole and protrudes out of the dielectric layer. The contact plug includes a lower portion and an upper portion. The lower portion fills in the contact hole. The upper portion is outside of the contact hole. The upper portion has a top side and a bottom side greater than the top side. The top side and the bottom side are parallel. The bottom side is closer to the contact hole than the top side. An MRAM is disposed on the contact hole and contacts the contact plug.
    Type: Application
    Filed: February 19, 2019
    Publication date: July 16, 2020
    Inventors: Yi-Hui Lee, I-Ming Tseng, Ying-Cheng Liu, Yi-An Shih, Yu-Ping Wang
  • Publication number: 20200227625
    Abstract: A magneto-resistive random access memory (MRAM) cell includes a substrate having a dielectric layer disposed thereon, a conductive via disposed in the dielectric layer, and a cylindrical stack disposed on the conductive via. The cylindrical stack includes a bottom electrode, a magnetic tunneling junction (MTJ) layer on the bottom electrode, and a top electrode on the MTJ layer. A spacer layer is disposed on a sidewall of the cylindrical stack. The top electrode protrudes from a top surface of the spacer layer.
    Type: Application
    Filed: January 29, 2019
    Publication date: July 16, 2020
    Inventors: Hui-Lin Wang, Yi-Wei Tseng, Meng-Jun Wang, Chen-Yi Weng, Chin-Yang Hsieh, Jing-Yin Jhang, Yu-Ping Wang, Chien-Ting Lin, Ying-Cheng Liu, Yi-An Shih, Yi-Hui Lee, I-Ming Tseng
  • Publication number: 20200185597
    Abstract: A memory device includes an insulation layer, a memory cell region and an alignment mark region are defined on the insulation layer, an interconnection structure disposed in the insulation layer, a dielectric layer disposed on the insulation layer and the interconnection structure, the dielectric layer is disposed within the memory cell region and the alignment mark region, a conductive via plug disposed on the interconnection structure within the memory cell region, the conductive via plug has a concave top surface, an alignment mark trench penetrating the dielectric layer within the alignment mark region, a bottom electrode disposed on the conductive via plug within the memory cell region and disposed in the alignment mark trench within the alignment mark region, and a magnetic tunnel junction (MTJ) structure disposed on the bottom electrode within the memory cell region and disposed in the alignment mark trench within the alignment mark region.
    Type: Application
    Filed: December 11, 2018
    Publication date: June 11, 2020
    Inventors: Kun-Ju Li, Hsin-Jung Liu, I-Ming Tseng, Chau-Chung Hou, Yu-Lung Shih, Fu-Chun Hsiao, Hui-Lin Wang, Tzu-Hsiang Hung, Chih-Yueh Li, Ang Chan, Jing-Yin Jhang
  • Publication number: 20200176331
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate.
    Type: Application
    Filed: February 5, 2020
    Publication date: June 4, 2020
    Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
  • Patent number: 10672979
    Abstract: A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the IMD layer; forming a bottom electrode layer on the IMD layer; forming a cap layer on the bottom electrode layer; and removing part of the cap layer, part of the bottom electrode layer, and part of the IMD layer to form a trench.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: June 2, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-An Shih, I-Ming Tseng, Yi-Hui Lee, Ying-Cheng Liu, Yu-Ping Wang
  • Patent number: 10658458
    Abstract: A method of forming a semiconductor structure is disclosed. A fin structure is formed on a substrate and a trench is formed in the fin structure. The trench has a top corner, an upper portion having an upper sidewall and a lower portion having a lower sidewall. A first dielectric layer is then formed on the substrate and fills the lower portion of the trench. After that, a second dielectric layer is formed on the substrate and covers the top corner and the upper sidewall of the trench. The second dielectric layer also covers an upper surface of the first dielectric layer.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: May 19, 2020
    Assignee: UNITED MICROELECTRONCIS CORP.
    Inventors: I-Ming Tseng, Chun-Hsien Lin, Wen-An Liang
  • Patent number: 10631638
    Abstract: A slide rail assembly includes a first rail, a second rail, and a reinforcing structure. The first rail includes a front end portion and a rear end portion. The second rail is displaceable with respect to the first rail. The reinforcing structure is located at the second rail. A portion of the reinforcing structure protrudes beyond the front end portion of the first rail when the second rail is displaced from a first position to a second position with respect to the first rail.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: April 28, 2020
    Assignees: King Slide Works Co., Ltd., King Slide Technology Co., Ltd.
    Inventors: Ken-Ching Chen, Shun-Ho Yang, I-Ming Tseng, Chun-Chiang Wang