Patents by Inventor I-Sheng Chen

I-Sheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11908749
    Abstract: A method includes: providing a first gate electrode over the substrate; forming a first pair of spacers on two sides of the first gate electrode; removing the first gate electrode to form a first trench between the first pair of spacers; depositing a dielectric layer in the first trench; depositing a first layer over the dielectric layer; removing the first layer from the first trench; and depositing a work function layer over the dielectric layer in the first trench.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi-Jing Lee, Ya-Yun Cheng, Hau-Yu Lin, I-Sheng Chen, Chia-Ming Hsu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Publication number: 20240047526
    Abstract: Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate and spaced apart from each other in a first direction. The semiconductor structure further includes a gate structure wrapping around the nanostructures and a semiconductor layer attached to the nanostructures in a second direction different from the first direction. The semiconductor structure further includes inner spacers sandwiched between the semiconductor layer and the gate structure in the second direction and a silicide layer formed over the semiconductor layer. In addition, a first portion of the semiconductor layer is sandwiched between the inner spacers and the silicide layer in the second direction.
    Type: Application
    Filed: October 16, 2023
    Publication date: February 8, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Ching CHENG, I-Sheng CHEN, Tzu-Chiang CHEN, Shih-Syuan HUANG, Hung-Li CHIANG
  • Patent number: 11894438
    Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yee-Chia Yeo, Sung-Li Wang, Chi On Chui, Jyh-Cherng Sheu, Hung-Li Chiang, I-Sheng Chen
  • Patent number: 11862732
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes providing a substrate having a first fin, and the first fin has a channel region and a source/drain region. The method includes forming a stack structure over the first fin, and the stack structure includes a first semiconductor layer and a second semiconductor layer vertically stacked over the fin. The method also includes removing a portion of the second semiconductor layer in the channel region, and a portion of the first semiconductor layer is remaining in the channel region. The method further includes forming a cladding layer over the remaining first semiconductor material layer in the channel region to form a nanostructure, wherein the nanostructure has a dumbbell shape. The method includes forming a gate structure surrounding the nanostructure.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wilman Tsai, Cheng-Hsien Wu, I-Sheng Chen, Stefan Rusu
  • Patent number: 11855151
    Abstract: A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: I-Sheng Chen, Cheng-Hsien Wu, Chih Chieh Yeh, Yee-Chia Yeo
  • Publication number: 20230412477
    Abstract: A data storage method and system, applied in a network system of distributed ledger technology. The method comprises: storing, by a first node, data of information units of the network system; determining, by a second node, a designated origin signal including an identifier of at least one origin information unit; obtaining, by the second node, data of the information units of the network system from the first node; determining, by the second node, a designated destination signal including an identifier of a destination information unit; determining, by the second node, a shortest path data from the origin information unit to the destination information unit according to the designated origin signal, the data of the information units of the network system, and the designated destination signal; and storing, by the second node, data of all information units included in the shortest path data.
    Type: Application
    Filed: June 16, 2022
    Publication date: December 21, 2023
    Inventors: Chu George Kai, I-Sheng Chen
  • Patent number: 11848242
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Li Chiang, Chih-Liang Chen, Tzu-Chiang Chen, I-Sheng Chen, Lei-Chun Chou
  • Publication number: 20230377984
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers containing Ge and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A Ge concentration in the first semiconductor layers is increased. A sacrificial gate structure is formed over the fin structure. A source/drain epitaxial layer is formed over a source/drain region of the fin structure. The sacrificial gate structure is removed. The second semiconductor layers in a channel region are removed, thereby releasing the first semiconductor layers in which the Ge concentration is increased. A gate structure is formed around the first semiconductor layers in which the Ge concentration is increased.
    Type: Application
    Filed: August 7, 2023
    Publication date: November 23, 2023
    Inventors: Chao-Ching CHENG, I-Sheng CHEN, Hung-Li CHIANG, Tzu-Chiang CHEN
  • Patent number: 11823957
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers containing Ge and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A Ge concentration in the first semiconductor layers is increased. A sacrificial gate structure is formed over the fin structure. A source/drain epitaxial layer is formed over a source/drain region of the fin structure. The sacrificial gate structure is removed. The second semiconductor layers in a channel region are removed, thereby releasing the first semiconductor layers in which the Ge concentration is increased. A gate structure is formed around the first semiconductor layers in which the Ge concentration is increased.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: November 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chao-Ching Cheng, I-Sheng Chen, Hung-Li Chiang, Tzu-Chiang Chen
  • Patent number: 11824088
    Abstract: Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and first nanostructures and second nanostructures formed over the substrate. The semiconductor structure further includes a first source/drain structure formed adjacent to the first nanostructures and a second source/drain structure formed adjacent to the second nanostructures. The semiconductor structure further includes a first contact plug formed over the first source/drain structure and a second contact plug formed over the second source/drain structure. In addition, a bottom portion of the first contact plug is lower than a bottom portion of the first nanostructures, and a bottom portion of the second contact plug is higher than a top portion of the second nanostructures.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: November 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Ching Cheng, I-Sheng Chen, Tzu-Chiang Chen, Shih-Syuan Huang, Hung-Li Chiang
  • Publication number: 20230343876
    Abstract: A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.
    Type: Application
    Filed: June 12, 2023
    Publication date: October 26, 2023
    Inventors: I-Sheng Chen, Chao-Ching Cheng, Tzu-Chiang Chen, Carlos H Diaz
  • Patent number: 11777008
    Abstract: A gate-all-around structure is provided. The gate-all-around structure includes a plurality of nanostructures stacked over a substrate in a vertically direction, and the nanostructures extends from a gate region to a source/drain (S/D) region. The gate-all-around structure includes a gate structure formed in the gate region around the first nanostructures, and a S/D structure formed in the S/D region. The S/D structure is in direct contact with a top surface of one of the nanostructures.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chao-Ching Cheng, Yu-Lin Yang, I-Sheng Chen, Tzu-Chiang Chen
  • Publication number: 20230298944
    Abstract: The present disclosure describes a method that includes forming a fin protruding from a substrate, the fin including a first sidewall and a second sidewall formed opposite to the first sidewall. The method also includes depositing a shallow-trench isolation (STI) material on the substrate. Depositing the STI material includes depositing a first portion of the STI material in contact with the first sidewall and depositing a second portion of the STI material in contact with the second sidewall. The method also includes performing a first etching process on the STI material to etch the first portion of the STI material at a first etching rate and the second portion of the STI material at a second etching rate greater than the first etching rate. The method also includes performing a second etching process on the STI material to etch the first portion of the STI material at a third etching rate and the second portion of the STI material at a fourth etching rate less than the third etching rate.
    Type: Application
    Filed: May 25, 2023
    Publication date: September 21, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: I-Sheng CHEN, Yi-Jing LI, Chen-Heng LI
  • Patent number: 11749526
    Abstract: A semiconductor substrate includes a first material layer made of a first material and including a plurality of protrusions, and a second material layer made of a second material different from the first material, filling spaces between the plurality of protrusions, and covering the plurality of protrusions. Each of the protrusions includes a tip and a plurality of facets converging at the tip, and adjacent facets of adjacent protrusions are in contact with each other.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: I-Sheng Chen, Tzu-Chiang Chen, Cheng-Hsien Wu
  • Patent number: 11715802
    Abstract: A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: August 1, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Sheng Chen, Chao-Ching Cheng, Tzu-Chiang Chen, Carlos H Diaz
  • Patent number: 11699620
    Abstract: The present disclosure describes a method that includes forming a fin protruding from a substrate, the fin including a first sidewall and a second sidewall formed opposite to the first sidewall. The method also includes depositing a shallow-trench isolation (STI) material on the substrate. Depositing the STI material includes depositing a first portion of the STI material in contact with the first sidewall and depositing a second portion of the STI material in contact with the second sidewall. The method also includes performing a first etching process on the STI material to etch the first portion of the STI material at a first etching rate and the second portion of the STI material at a second etching rate greater than the first etching rate. The method also includes performing a second etching process on the STI material to etch the first portion of the STI material at a third etching rate and the second portion of the STI material at a fourth etching rate less than the third etching rate.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: July 11, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: I-Sheng Chen, Yi-Jing Li, Chen-Heng Li
  • Publication number: 20230185294
    Abstract: An energy storage device includes a sensor, a communication circuit and a processor. The sensor is configured to detect an abnormal event occurred in the energy storage device. The communication circuit is configured to connect to a local area network. The local area network includes a plurality of nodes formed by the energy storage device and other energy storage devices. The processor is configured to generate, according to the abnormal event detected by the sensor, historical usage data recording the abnormal event. In response to a trigger event, the processor is further configured to: update the historical usage data; and control the communication circuit to transmit at least part of the updated historical usage data to at least one energy storage device adjacent to the energy storage device in the local area network.
    Type: Application
    Filed: December 14, 2022
    Publication date: June 15, 2023
    Inventors: Liang-Yi Hsu, I-Sheng Chen, Yong-Sheng Chen, Wei-Tsung Huang
  • Publication number: 20230187552
    Abstract: A multi-gate semiconductor device includes a plurality of nanostructures vertically stacked over a substrate, a gate dielectric layer wrapping around the plurality of nanostructures, a gate conductive structure over the gate dielectric layer, and a first insulating spacer alongside the gate conductive structure and over the plurality of nanostructures. The first insulating spacer is in direct contact with the gate conductive structure and the gate dielectric layer.
    Type: Application
    Filed: February 6, 2023
    Publication date: June 15, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Sheng CHEN, Tzu-Chiang CHEN, Cheng-Hsien WU, Ling-Yen YEH, Carlos H. DIAZ
  • Publication number: 20230087836
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a fin structure over the substrate. The fin structure has a channel height. The semiconductor device structure also includes a stack of nanostructures over the substrate. The channel height is greater than a lateral distance between the fin structure and the stack of the nanostructures. The semiconductor device structure further includes a metal gate stack over the nanostructures, and the nanostructures are separated from each other by portions of the metal gate stack. In addition, the semiconductor device structure includes a dielectric layer surrounding the metal gate stack, the nanostructures, and the fin structure.
    Type: Application
    Filed: November 28, 2022
    Publication date: March 23, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Li CHIANG, I-Sheng CHEN, Tzu-Chiang CHEN
  • Publication number: 20230079483
    Abstract: A method includes: providing a first gate electrode over the substrate; forming a first pair of spacers on two sides of the first gate electrode; removing the first gate electrode to form a first trench between the first pair of spacers; depositing a dielectric layer in the first trench; depositing a first layer over the dielectric layer; removing the first layer from the first trench; and depositing a work function layer over the dielectric layer in the first trench.
    Type: Application
    Filed: November 21, 2022
    Publication date: March 16, 2023
    Inventors: YI-JING LEE, YA-YUN CHENG, HAU-YU LIN, I-SHENG CHEN, CHIA-MING HSU, CHIH-HSIN KO, CLEMENT HSINGJEN WANN