Abstract: A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material.

Abstract: Disclosed is a power storage device and method for discharging the same, which configures the power storage device to perform an electric power output under a discharging limit upon coupling with a load device and before any authentication is conducted. The discharging limit for the electric power output will be lifted only when an authentication result between the power storage device and the load device indicates a successful authentication.

Abstract: A semiconductor structure includes a first metal-dielectric-metal layer, a first dielectric layer, a first conductive layer, a second conductive layer, and a second dielectric layer. The first metal-dielectric-metal layer includes a plurality of first fingers, a plurality of second fingers, and a first dielectric material. The first fingers are electrically connected to a first voltage. The second fingers are electrically connected to a second voltage different from the first voltage, and the first fingers and the second fingers are arranged in parallel and staggeredly. The first dielectric material is between the first fingers and the second fingers. The first dielectric layer is over the first metal-dielectric-metal layer. The first conductive layer is over the first dielectric layer. The second conductive layer is over the first conductive layer. The second dielectric layer is between the first conductive layer and the second conductive layer.

Abstract: An antenna module includes a first antenna radiator including a feeding terminal, a second antenna radiator, a first ground radiator, a second ground radiator and a capacitive element. The second antenna radiator is disposed on one side of the first antenna radiator, and a first gap is formed between a main portion of the second antenna radiator and the first antenna radiator. The first ground radiator is disposed on another side of the first antenna radiator, and a second gap is formed between the first antenna radiator and the first antenna radiator. The second ground radiator is disposed between the second antenna radiator and the first ground radiator, and a third gap is formed between the second ground radiator and a first branch of the second antenna radiator. The capacitive element is disposed on the third gap and connects the second antenna radiator and the second ground radiator.

Abstract: A display device including a first light emitting unit, a second light emitting unit, a first optical layer and a second optical layer is disclosed. The first optical layer is disposed on at least one of the first light emitting unit and the second light emitting unit, and the first optical layer includes a collimating layer. The second optical layer is disposed on the first light emitting unit. The second optical layer is configured to scatter a first light emitted from the first light emitting unit but does not scatter a second light emitted from the second light emitting unit.

Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.

Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure further includes a gate structure surrounding the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure further includes a contact formed over the source/drain structure and extending into the source/drain structure.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure.

Abstract: Aspects of the present disclosure provide a method for training a predictor that predicts performance of a plurality of machine learning (ML) models on platforms. For example, the method can include converting each of the ML models into a plurality of instructions or the instructions and a plurality of intermediate representations (IRs). The method can also include simulating execution of the instructions corresponding to each of the ML models on a platform and generating instruction performance reports. Each of the instruction performance reports can be associated with performance of the instructions corresponding to one of the ML models that are executed on the platform. The method can also include training the predictor with the instructions or the IRs as learning features and the instruction performance reports as learning labels, compiling the predictor into a library file, and storing the library file in a storage device.

Abstract: A method includes: providing a first gate electrode over the substrate; forming a first pair of spacers on two sides of the first gate electrode; removing the first gate electrode to form a first trench between the first pair of spacers; depositing a dielectric layer in the first trench; depositing a first layer over the dielectric layer; removing the first layer from the first trench; and depositing a work function layer over the dielectric layer in the first trench.

Abstract: Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate and spaced apart from each other in a first direction. The semiconductor structure further includes a gate structure wrapping around the nanostructures and a semiconductor layer attached to the nanostructures in a second direction different from the first direction. The semiconductor structure further includes inner spacers sandwiched between the semiconductor layer and the gate structure in the second direction and a silicide layer formed over the semiconductor layer. In addition, a first portion of the semiconductor layer is sandwiched between the inner spacers and the silicide layer in the second direction.

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes providing a substrate having a first fin, and the first fin has a channel region and a source/drain region. The method includes forming a stack structure over the first fin, and the stack structure includes a first semiconductor layer and a second semiconductor layer vertically stacked over the fin. The method also includes removing a portion of the second semiconductor layer in the channel region, and a portion of the first semiconductor layer is remaining in the channel region. The method further includes forming a cladding layer over the remaining first semiconductor material layer in the channel region to form a nanostructure, wherein the nanostructure has a dumbbell shape. The method includes forming a gate structure surrounding the nanostructure.

Abstract: A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material.

Abstract: A data storage method and system, applied in a network system of distributed ledger technology. The method comprises: storing, by a first node, data of information units of the network system; determining, by a second node, a designated origin signal including an identifier of at least one origin information unit; obtaining, by the second node, data of the information units of the network system from the first node; determining, by the second node, a designated destination signal including an identifier of a destination information unit; determining, by the second node, a shortest path data from the origin information unit to the destination information unit according to the designated origin signal, the data of the information units of the network system, and the designated destination signal; and storing, by the second node, data of all information units included in the shortest path data.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers containing Ge and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A Ge concentration in the first semiconductor layers is increased. A sacrificial gate structure is formed over the fin structure. A source/drain epitaxial layer is formed over a source/drain region of the fin structure. The sacrificial gate structure is removed. The second semiconductor layers in a channel region are removed, thereby releasing the first semiconductor layers in which the Ge concentration is increased. A gate structure is formed around the first semiconductor layers in which the Ge concentration is increased.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers containing Ge and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A Ge concentration in the first semiconductor layers is increased. A sacrificial gate structure is formed over the fin structure. A source/drain epitaxial layer is formed over a source/drain region of the fin structure. The sacrificial gate structure is removed. The second semiconductor layers in a channel region are removed, thereby releasing the first semiconductor layers in which the Ge concentration is increased. A gate structure is formed around the first semiconductor layers in which the Ge concentration is increased.

Abstract: Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and first nanostructures and second nanostructures formed over the substrate. The semiconductor structure further includes a first source/drain structure formed adjacent to the first nanostructures and a second source/drain structure formed adjacent to the second nanostructures. The semiconductor structure further includes a first contact plug formed over the first source/drain structure and a second contact plug formed over the second source/drain structure. In addition, a bottom portion of the first contact plug is lower than a bottom portion of the first nanostructures, and a bottom portion of the second contact plug is higher than a top portion of the second nanostructures.

Abstract: A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.