Abstract: Embodiments of the present disclosure provide a method for forming a semiconductor device structure. The method includes forming a fin structure over a substrate, forming an insulating material adjacent the fin structure, depositing a gate dielectric layer over the fin structure and the insulating material, depositing a gate electrode layer on the gate dielectric layer, forming an opening through the gate electrode layer and the gate dielectric layer into the insulating material, then performing an etch process that etches the gate dielectric layer at a faster rate than the gate electrode layer, and filling the opening with a dielectric material.

Abstract: A method includes: providing a substrate containing a first plurality of fins of a first polarity type, a second plurality of fins of a second polarity type, and a contiguous gate structure that extends over each of the first plurality of fins and second plurality of fins; and forming a first opening in the contiguous gate structure with a first cut between the first pair of fins of the first polarity type and a second opening in the contiguous gate structure with a second cut between the second pair of fins of the second polarity type via common etching operations; wherein performing the common etching operations includes forming the first opening with a first middle critical dimension (MCD) and the second opening with a second MCD, wherein the first MCD is larger than the second MCD.

Abstract: Methods for etching metal, such as for processing a metal gate, are provided. A method includes forming a hard mask over the metal, wherein the hard mask includes a sidewall defining an opening; and performing a plasma etching process including cycles of depositing a carbon nitride film on the sidewall and etching the metal.

Abstract: A semiconductor device and method of forming thereof includes a first fin and a second fin each extending from a substrate. A first gate segment is disposed over the first channel and a second gate segment is disposed over the second channel. An interlayer dielectric (ILD) layer is adjacent the first gate segment and the second gate segment. A cut region (e.g., opening or gap between first gate structure and the second gate structure) extends between the first and second gate segments. The cut region has a first portion has a first width and a second portion has a second width, the second width is greater than the first width. The second portion interposes the first and second gate segments and the first portion is defined within the ILD layer.

Abstract: A method that include forming a plurality of semiconductor regions having first lengthwise directions parallel to a first direction, and forming a plurality of gate stacks having second lengthwise directions parallel to a second direction perpendicular to the first direction, wherein the plurality of gate stacks are on first portions of the plurality of semiconductor regions. The method can also include etching the plurality of semiconductor regions to form a first plurality of openings, and filling the first plurality of openings with a first dielectric material to form fin isolation regions. The method can also include forming an isolation interface region between the fin isolation regions and the gate stacks.

Abstract: A semiconductor device and method of forming thereof includes a first fin and a second fin each extending from a substrate. A first gate segment is disposed over the first channel and a second gate segment is disposed over the second channel. An interlayer dielectric (ILD) layer is adjacent the first gate segment and the second gate segment. A cut region (e.g., opening or gap between first gate structure and the second gate structure) extends between the first and second gate segments. The cut region has a first portion has a first width and a second portion has a second width, the second width is greater than the first width. The second portion interposes the first and second gate segments and the first portion is defined within the ILD layer.

Abstract: Embodiments of the present disclosure provide a method for forming a semiconductor device structure. The method includes forming a fin structure over a substrate, forming an insulating material adjacent the fin structure, depositing a gate dielectric layer over the fin structure, depositing a gate electrode layer on the gate dielectric layer, and forming an opening through the gate electrode layer and the gate dielectric layer into the insulating material by a cyclic process. The cyclic process includes performing a first number of cycles, each cycle of the first number of cycles includes a first main etch process having a first plasma bias voltage, performing a second number of cycles, and each cycle of the second number of cycles includes a second main etch process having a second plasma bias voltage substantially greater than the first plasma bias voltage. The method further includes filling the opening with a dielectric material.

Abstract: A semiconductor structure includes a substrate, first and second channels, first and second gate structures, first source/drain structures, second source/drain structures, a separation plug, and an isolation material. The first and second channels are on the substrate. The first gate structure is across the first channel. The second gate structure is across the second channel. The first source/drain structures are on opposite sides of the first channel. The second source/drain structures are on opposite sides of the second channel. The separation plug has a first separation portion between the first and second gate structures and second and third separation portions extending laterally from the first separation portion beyond opposite sidewalls of the first gate structure in a top view. The isolation material surrounds one of the second and third separation portions in the top view.

Abstract: Embodiments of the present disclosure provide a method for forming a semiconductor device structure. The method includes forming a fin structure over a substrate, forming an insulating material adjacent the fin structure, depositing a gate dielectric layer over the fin structure and the insulating material, depositing a gate electrode layer on the gate dielectric layer, forming an opening through the gate electrode layer and the gate dielectric layer into the insulating material, then performing an etch process that etches the gate dielectric layer at a faster rate than the gate electrode layer, and filling the opening with a dielectric material.

Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first dielectric layer over the substrate. The semiconductor device structure also includes a first metal gate stack and a second metal gate stack over the substrate and the first dielectric layer. The semiconductor device structure further includes a second dielectric layer beside the first metal gate stack and an insulating structure over the substrate. A portion of the insulating structure is between the first metal gate stack and the second metal gate stack. The insulating structure penetrates into the second dielectric layer.

Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.

Abstract: Methods for etching metal, such as for processing a metal gate, are provided. A method includes forming a hard mask over the metal, wherein the hard mask includes a sidewall defining an opening; and performing a plasma etching process including cycles of depositing a carbon nitride film on the sidewall and etching the metal.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a first conductive material and a second conductive material disposed over the semiconductor substrate and the first dielectric layer. The semiconductor device structure further includes a second dielectric layer surrounding the first conductive material and the second conductive material and an insulating structure over the semiconductor substrate. The insulating structure is disposed between the first conductive material and the second conductive material. The insulating structure comprises a material different from the first dielectric layer and the second dielectric layer.

Abstract: A method includes forming a first fin and a second fin on a substrate; forming a dummy gate material over the first fin and the second fin; etching the dummy gate material using a first etching process to form a recess between the first fin and the second fin, wherein a sacrificial material is formed on sidewalls of the recess during the first etching process; filling the recess with an insulation material; removing the dummy gate material and the sacrificial material using a second etching process; and forming a first replacement gate over the first fin and a second replacement gate over the second fin, wherein the first replacement gate is separated from the second replacement gate by the insulation material.

Abstract: A semiconductor device includes a first and a second semiconductor fins extending along a first direction; an isolation region disposed between respective lower portions of the first and second semiconductor fins; a dielectric structure disposed between the first and the second semiconductor fins and above the isolation region, with a bottom surface aligned with a top surface of the isolation region; a gate isolation structure vertically disposed above the dielectric structure; and a metal gate layer extending along a second direction perpendicular to the first direction. The metal gate layer includes a first portion straddling the first semiconductor fin and a second portion straddling the second semiconductor fin. The gate isolation structure separates the first and second portions of the metal gate layer from each other and includes a top portion vertically extending above the dielectric structure and a bottom portion extending into the dielectric structure.

Abstract: An anchored cut-metal gate (CMG) plug, a semiconductor device including the anchored CMG plug and methods of forming the semiconductor device are disclosed herein. The method includes performing a series of etching processes to form a trench through a metal gate electrode, through an isolation region, and into a semiconductor substrate. The trench cuts-through and separates the metal gate electrode into a first metal gate and a second metal gate and forms a recess in the semiconductor substrate. Once the trench has been formed, a dielectric plug material is deposited into the trench to form a CMG plug that is anchored within the recess of the semiconductor substrate and separates the first and second metal gates. As such, the anchored CMG plug provides high levels of resistance to reduce leakage current within the semiconductor device during operation and allowing for improved V-trigger performance of the semiconductor device.

Abstract: An anchored cut-metal gate (CMG) plug, a semiconductor device including the anchored CMG plug and methods of forming the semiconductor device are disclosed herein. The method includes performing a series of etching processes to form a trench through a metal gate electrode, through an isolation region, and into a semiconductor substrate. The trench cuts-through and separates the metal gate electrode into a first metal gate and a second metal gate and forms a recess in the semiconductor substrate. Once the trench has been formed, a dielectric plug material is deposited into the trench to form a CMG plug that is anchored within the recess of the semiconductor substrate and separates the first and second metal gates. As such, the anchored CMG plug provides high levels of resistance to reduce leakage current within the semiconductor device during operation and allowing for improved V-trigger performance of the semiconductor device.

Abstract: A semiconductor device includes a first semiconductor fin extending along a first direction. The semiconductor device includes a second semiconductor fin also extending along the first direction. The semiconductor device includes a dielectric structure disposed between the first and second semiconductor fins. The semiconductor device includes a gate isolation structure vertically disposed above the dielectric structure. The semiconductor device includes a metal gate layer extending along a second direction perpendicular to the first direction, wherein the metal gate layer includes a first portion straddling the first semiconductor fin and a second portion straddling the second semiconductor fin. The gate isolation structure separates the first and second portions of the metal gate layer from each other and includes a bottom portion extending into the dielectric structure.

Abstract: A method includes forming a first fin and a second fin on a substrate; forming a dummy gate material over the first fin and the second fin; etching the dummy gate material using a first etching process to form a recess between the first fin and the second fin, wherein a sacrificial material is formed on sidewalls of the recess during the first etching process; filling the recess with an insulation material; removing the dummy gate material and the sacrificial material using a second etching process; and forming a first replacement gate over the first fin and a second replacement gate over the second fin, wherein the first replacement gate is separated from the second replacement gate by the insulation material.