Abstract: A method for forming a semiconductor device structure includes forming a first dummy gate stack and a second dummy gate stack over a semiconductor substrate and forming a dielectric layer over the semiconductor substrate to surround the first dummy gate stack and the second dummy gate stack. The method includes removing the first dummy gate stack and the second dummy gate stack to form a first trench and a second trench in the dielectric layer and removing the first dummy gate stack and the second dummy gate stack to form a first trench and a second trench in the dielectric layer. The method includes partially removing the first metal gate stack, the second metal gate stack, and the dielectric layer to form a recess. The method includes forming an insulating structure to partially or completely fill the recess.

Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.

Abstract: A method for forming a semiconductor device structure includes forming a first dummy gate stack and a second dummy gate stack over a semiconductor substrate and forming a dielectric layer over the semiconductor substrate to surround the first dummy gate stack and the second dummy gate stack. The method includes removing the first dummy gate stack and the second dummy gate stack to form a first trench and a second trench in the dielectric layer and removing the first dummy gate stack and the second dummy gate stack to form a first trench and a second trench in the dielectric layer. The method includes partially removing the first metal gate stack, the second metal gate stack, and the dielectric layer to form a recess. The method includes forming an insulating structure to partially or completely fill the recess.

Abstract: A semiconductor structure with cutting depth control and method for fabricating the same are provided. In the method for fabricating the semiconductor device, at first, fins protruding from a substrate are formed. Next, source/drain devices are grown on both ends of the fins. Then, an inter-layer dielectric layer crossing the fins and enclosing the source/drain devices is deposited. A metal gate structure enclosed by the inter-layer dielectric layer is formed between the source/drain devices. And then, a replacement operation is performed to replace a portion of the inter-layer dielectric layer with an isolation material, thereby forming an isolation portion that adjoins the metal gate structure and is located between the adjacent source/drain devices. Thereafter, a metal gate cut operation is performed, thereby forming an opening in the metal gate structure and an opening in the isolation portion, and an insulating material is deposited in the openings.

Abstract: A semiconductor device and method of forming thereof includes a first fin and a second fin each extending from a substrate. A first gate segment is disposed over the first fin and a second gate segment is disposed over the second fin. An interlayer dielectric (ILD) layer is adjacent the first gate segment and the second gate segment. A cut region (e.g., opening or gap between first gate structure and the second gate structure) extends between the first and second gate segments. The cut region has a first portion has a first width and a second portion has a second width, the second width is greater than the first width. The second portion interposes the first and second gate segments and the first portion is defined within the ILD layer.