Patents by Inventor Ian A. Swarbrick
Ian A. Swarbrick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230376248Abstract: Examples of the present disclosure generally relate to integrated circuits, such as a system-on-chip (SoC), that include a memory subsystem. In some examples, an integrated circuit includes a first master circuit in a first power domain on a chip; a second master circuit in a second power domain on the chip; and a first memory controller in a third power domain on the chip. The first master circuit and the second master circuit each are configured to access memory via the first memory controller. The first power domain and the second power domain each are separate and independent from the third power domain.Type: ApplicationFiled: July 25, 2023Publication date: November 23, 2023Inventors: Ygal ARBEL, Ian A. SWARBRICK, Sagheer AHMAD
-
Publication number: 20230291405Abstract: A System-on-Chip includes a data processing engine array. The data processing engine array includes a plurality of data processing engines organized in a grid. The plurality of data processing engines are partitioned into at least a first partition and a second partition. The first partition includes one or more first data processing engines of the plurality of data processing engines. The second partition includes one or more second data processing engines of the plurality of data processing engines. Each partition is configured to implement an application that executes independently of the other partition.Type: ApplicationFiled: May 18, 2023Publication date: September 14, 2023Applicant: Xilinx, Inc.Inventors: Sagheer Ahmad, Jaideep Dastidar, Brian C. Gaide, Juan J. Noguera Serra, Ian A. Swarbrick
-
Patent number: 11709624Abstract: Examples of the present disclosure generally relate to integrated circuits, such as a system-on-chip (SoC), that include a memory subsystem. In some examples, an integrated circuit includes a first master circuit in a first power domain on a chip; a second master circuit in a second power domain on the chip; and a first memory controller in a third power domain on the chip. The first master circuit and the second master circuit each are configured to access memory via the first memory controller. The first power domain and the second power domain each are separate and independent from the third power domain.Type: GrantFiled: February 15, 2018Date of Patent: July 25, 2023Assignee: XILINX, INC.Inventors: Ygal Arbel, Ian A. Swarbrick, Sagheer Ahmad
-
Patent number: 11683038Abstract: A System-on-Chip includes a first partition configured to implement a first application using of at least a first portion of one or more of a plurality of subsystems of the System-on-Chip and a second partition configured to implement a second application concurrently with the first partition. The second application uses at least a second portion of one or more of the plurality of subsystems. The first partition is isolated from the second partition.Type: GrantFiled: June 17, 2021Date of Patent: June 20, 2023Assignee: Xilinx, Inc.Inventors: Sagheer Ahmad, Jaideep Dastidar, Brian C. Gaide, Juan J. Noguera Serra, Ian A. Swarbrick
-
Patent number: 11281810Abstract: Examples described herein provide for memory access protection in programmable logic devices. In an example, an integrated circuit includes a programmable logic region, control logic, an interconnect, and a memory controller. The control logic is communicatively coupled to the programmable logic region. The control logic is configurable to generate one or more transaction attributes of a memory transaction request, and the memory transaction request is communicated from the programmable logic region. The interconnect is communicatively coupled to the control logic. The interconnect is operable to communicate the memory transaction request therethrough. The memory controller is communicatively coupled to the interconnect. The memory controller is operable to receive the memory transaction request. The memory controller is configurable to determine whether the memory transaction request is permitted based on the one or more transaction attributes.Type: GrantFiled: December 11, 2018Date of Patent: March 22, 2022Assignee: XILINX, INC.Inventor: Ian A. Swarbrick
-
Patent number: 11063594Abstract: An integrated circuit (IC) includes a first interface configured for operation with a plurality of tenants implemented concurrently in the integrated circuit, wherein the plurality of tenants communicate with a host data processing system using the first interface. The IC includes a second interface configured for operation with the plurality of tenants, wherein the plurality of tenants communicate with one or more network nodes via a network using the second interface. The IC can include a programmable logic circuitry configured for operation with the plurality of tenants, wherein the programmable logic circuitry implements one or more hardware accelerated functions for the plurality of tenants and routes data between the first interface and the second interface. The first interface, the second interface, and the programmable logic circuitry are configured to provide isolation among the plurality of tenants.Type: GrantFiled: May 11, 2020Date of Patent: July 13, 2021Assignee: Xilinx, Inc.Inventors: Sagheer Ahmad, Jaideep Dastidar, Brian C. Gaide, Juan J. Noguera Serra, Ian A. Swarbrick
-
Patent number: 10963421Abstract: Embodiments herein describe a SoC that includes a mapper that identifies a destination ID for routing a transaction through a NoC. In one embodiment, the NoC includes ingress and egress logic blocks which permit hardware elements in the SoC to transmit and receive data using the NoC. In one embodiment, the ingress logic blocks can include the mapper that identifies a destination ID for each transaction. In one embodiment, the mapper can receive a destination ID from the hardware element that submitted the transaction to the ingress logic block. In this case, the mapper can bypass the address map by using the provided destination ID. If a destination ID is not provided, however, the mapper can use an address provided in the transaction to identify the destination ID.Type: GrantFiled: April 27, 2018Date of Patent: March 30, 2021Assignee: XILINX, INC.Inventor: Ian A. Swarbrick
-
Patent number: 10936486Abstract: Techniques for providing address interleave support in a programmable device are described. In an example, a programmable integrated circuit (IC) includes a processing system, programmable logic, a plurality of master circuits disposed in the processing system, the programmable logic, or both the processing system and the programmable logic, an address interleave and transaction chopping circuit, a memory having a plurality of channels, and a system interconnect configured to couple the address interleave and transaction chopping circuit to the memory. The address interleave and transaction chopping circuit is configured to interleave memory transactions from the plurality of master circuits across the plurality of channels of the memory at a selected boundary.Type: GrantFiled: February 21, 2019Date of Patent: March 2, 2021Assignee: XILINX, INC.Inventor: Ian A. Swarbrick
-
Patent number: 10893005Abstract: Examples described herein provide for an electronic circuit, such as a System-on-Chip (SoC), having a Network-on-Chip (NoC). The NoC is configurable and has capabilities to be partially reconfigured. In an example, a NoC on an integrated circuit is configured. Subsystems on the integrated circuit communicate via the NoC. The NoC is partially reconfigured. A first subset of the NoC is reconfigured during the partial reconfiguration, and a second subset of the NoC is capable of continuing to pass communications uninterruptedly during the partial reconfiguration. After the partial reconfiguration, two or more of the subsystems communicate via the first subset of the NoC.Type: GrantFiled: September 17, 2018Date of Patent: January 12, 2021Assignee: XILINX, INC.Inventors: David P. Schultz, Ian A. Swarbrick, Jun Liu, Raymond Kong, Herve Alexanian
-
Patent number: 10838908Abstract: An example programmable integrated circuit (IC) includes a processor, a plurality of endpoint circuits, a network-on-chip (NoC) having NoC master units (NMUs), NoC slave units (NSUs), NoC programmable switches (NPSs), a plurality of registers, and a NoC programming interface (NPI). The processor is coupled to the NPI and is configured to program the NPSs by loading an image to the registers through the NPI for providing physical channels between NMUs to the NSUs and providing data paths between the plurality of endpoint circuits.Type: GrantFiled: July 20, 2018Date of Patent: November 17, 2020Assignee: XILINX, INC.Inventors: Ian A. Swarbrick, Sagheer Ahmad, Ygal Arbel, Dinesh D. Gaitonde
-
Patent number: 10824505Abstract: An example multi-master system in a system-on-chip (SoC) includes a plurality of master circuits, an error-correcting code (ECC) proxy bridge comprising hardened circuitry in the SoC, a local interconnect configured to couple the plurality of master circuits to the ECC proxy bridge, a memory not having ECC support, and a system interconnect configured to couple the ECC proxy bridge to the memory. The ECC proxy bridge is configured to establish an ECC proxy region in the memory and, for each write transaction from the plurality of master circuits that targets the ECC proxy region, calculate and insert ECC bytes into the respective write transaction.Type: GrantFiled: August 21, 2018Date of Patent: November 3, 2020Assignee: XILINX, INC.Inventors: Ian A. Swarbrick, Nishit Patel
-
Patent number: 10817455Abstract: Examples herein describe a peripheral I/O device with a hybrid gateway that permits the device to have both I/O and coherent domains. That is, the I/O device can benefit from a traditional I/O model where the I/O device driver manages some of the compute resources in the I/O device as well as the benefits of adding other compute resources in the I/O device to the same coherent domain used by the hardware in the host computing system. As result, the compute resources in the coherent domain of the peripheral I/O device can communicate with the host in a similar manner as, e.g., CPU-to-CPU communication in the host. At the same time, the compute resources in the I/O domain can benefit from the advantages of the traditional I/O device model which provides efficiencies when doing large memory transfers between the host and the I/O device (e.g., DMA).Type: GrantFiled: April 10, 2019Date of Patent: October 27, 2020Assignee: XILINX, INC.Inventors: Jaideep Dastidar, Sagheer Ahmad, Ian A. Swarbrick
-
Publication number: 20200327089Abstract: Examples herein describe a peripheral I/O device with a hybrid gateway that permits the device to have both I/O and coherent domains. That is, the I/O device can benefit from a traditional I/O model where the I/O device driver manages some of the compute resources in the I/O device as well as the benefits of adding other compute resources in the I/O device to the same coherent domain used by the hardware in the host computing system. As result, the compute resources in the coherent domain of the peripheral I/O device can communicate with the host in a similar manner as, e.g., CPU-to-CPU communication in the host. At the same time, the compute resources in the I/O domain can benefit from the advantages of the traditional I/O device model which provides efficiencies when doing large memory transfers between the host and the I/O device (e.g., DMA).Type: ApplicationFiled: April 10, 2019Publication date: October 15, 2020Applicant: Xilinx, Inc.Inventors: Jaideep Dastidar, Sagheer Ahmad, Ian A. Swarbrick
-
Patent number: 10680615Abstract: A circuit for configuring function blocks of an integrated circuit device is described. The circuit comprises a processing system; a peripheral interface bus coupled to the processing system; and a function block coupled to the peripheral interface bus, the function block having programming registers and a function block core; wherein the programming registers store data determining a functionality of the function block core and comprise programming control registers enabling a configuration of the function block core using the data. A method of configuring function blocks of an integrated circuit device is also described.Type: GrantFiled: March 27, 2019Date of Patent: June 9, 2020Assignee: XILINX, INC.Inventors: David P. Schultz, Ian A. Swarbrick, Nagendra Donepudi
-
Patent number: 10673745Abstract: An example method of generating a configuration for a network on chip (NoC) in a programmable device includes: receiving traffic flow requirements for a plurality of traffic flows; assigning routes through the NoC for each traffic flow based on the traffic flow requirements; determining arbitration settings for the traffic flows along the assigned routes; generating programming data for the NoC; and loading the programming data to the programmable device to configure the NoC.Type: GrantFiled: February 1, 2018Date of Patent: June 2, 2020Assignee: XILINX, INC.Inventors: Ian A. Swarbrick, Ygal Arbel, Millind Mittal, Sagheer Ahmad
-
Patent number: 10673439Abstract: A device can include programmable logic circuitry, a processor system coupled to the programmable logic circuitry, and a network-on-chip. The network-on-chip is coupled to the programmable logic circuitry and the processor system. The network-on-chip is programmable to establish user specified data paths communicatively linking a circuit block implemented in the programmable logic circuitry and the processor system. The programmable logic circuitry, the network-on-chip, and the processor system are configured using a platform management controller.Type: GrantFiled: March 27, 2019Date of Patent: June 2, 2020Assignee: Xilinx, Inc.Inventors: Sagheer Ahmad, Jaideep Dastidar, Brian C. Gaide, Juan J. Noguera Serra, Ian A. Swarbrick
-
Patent number: 10628547Abstract: Routing a circuit design for implementation in an integrated circuit having a programmable network on chip can include determining Quality of Service (QOS) parameters for data flows of a circuit design, wherein the data flows involve transfers of data between masters and slaves through the programmable network on chip and generating, using a processor, an expression having a plurality of variables representing the data flows, routing constraints, and the QOS parameters. A routing solution can be determined using the processor for the data flows of the circuit design by initiating execution of a SAT solver using the expression.Type: GrantFiled: June 30, 2017Date of Patent: April 21, 2020Assignee: XILINX, INC.Inventors: Ian A. Swarbrick, Dinesh D. Gaitonde, Henri Fraisse
-
Patent number: 10621132Abstract: Embodiments herein describe techniques for assigning address ranges to ports in switches forming a packet protocol switch network in an integrated circuit. Instead of relying on a designer to provide the addresses, the integrated circuit can include an address bus which is incremented as addresses are assigned to the ports. In one embodiment, the port addresses are assigned from a root device and defines the address range of each branch port and the address of each endpoint in the network. As the address bus reaches an endpoint, an adder in the endpoint increments the value of the address bus (e.g., the current address). The address bus may use serial or parallel data communication to assign the addresses. In another embodiment, instead of using a separate address bus, a data bus typically used for packet communication assigns the addresses to the ports in the network.Type: GrantFiled: May 5, 2017Date of Patent: April 14, 2020Assignee: XILINX, INC.Inventors: Rafael C. Camarota, Ian A. Swarbrick, Kin Yip Sit
-
Patent number: 10621129Abstract: A peripheral interconnect for configuring slave endpoint circuits, such as may be in a configurable network, in a system-on-chip (SoC) is described herein. In an example, an apparatus includes a processing system on a chip, a circuit block on the chip, and a configurable network on the chip. The processing system and the circuit block are connected to the configurable network. The configurable network includes a peripheral interconnect. The peripheral interconnect includes a root node and a plurality of switches. The root node and the plurality of switches are connected in a tree topology. First branches of the tree topology are connected to respective slave endpoint circuits of the configurable network. The slave endpoint circuits of the configurable network are programmable to configure the configurable network.Type: GrantFiled: March 27, 2018Date of Patent: April 14, 2020Assignee: XILINX, INC.Inventors: Ian A. Swarbrick, David P. Schultz
-
Publication number: 20200092230Abstract: Examples described herein provide for an electronic circuit, such as a System-on-Chip (SoC), having a Network-on-Chip (NoC). The NoC is configurable and has capabilities to be partially reconfigured. In an example, a NoC on an integrated circuit is configured. Subsystems on the integrated circuit communicate via the NoC. The NoC is partially reconfigured. A first subset of the NoC is reconfigured during the partial reconfiguration, and a second subset of the NoC is capable of continuing to pass communications uninterruptedly during the partial reconfiguration. After the partial reconfiguration, two or more of the subsystems communicate via the first subset of the NoC.Type: ApplicationFiled: September 17, 2018Publication date: March 19, 2020Applicant: Xilinx, Inc.Inventors: David P. Schultz, Ian A. Swarbrick, Jun Liu, Raymond Kong, Herve Alexanian