Abstract: Examples described herein provide for an electronic circuit, such as a System-on-Chip (SoC), having a Network-on-Chip (NoC). The NoC is configurable and has capabilities to be partially reconfigured. In an example, a NoC on an integrated circuit is configured. Subsystems on the integrated circuit communicate via the NoC. The NoC is partially reconfigured. A first subset of the NoC is reconfigured during the partial reconfiguration, and a second subset of the NoC is capable of continuing to pass communications uninterruptedly during the partial reconfiguration. After the partial reconfiguration, two or more of the subsystems communicate via the first subset of the NoC.

Abstract: An example programmable integrated circuit (IC) includes a processor, a plurality of endpoint circuits, a network-on-chip (NoC) having NoC master units (NMUs), NoC slave units (NSUs), NoC programmable switches (NPSs), a plurality of registers, and a NoC programming interface (NPI). The processor is coupled to the NPI and is configured to program the NPSs by loading an image to the registers through the NPI for providing physical channels between NMUs to the NSUs and providing data paths between the plurality of endpoint circuits.

Abstract: Embodiments herein describe a SoC that includes a programmable NoC that can be reconfigured to support different interface communication protocols. In one embodiment, the NoC includes ingress and egress logic blocks which permit hardware elements in the SoC (e.g., processors, memory, programmable logic blocks, etc.) to transmit and receive data using the NoC. The ingress and egress logic blocks may first be configured to support a particular communication protocol for interfacing with the hardware elements. However, at a later time, the user may wish to reconfigure the ingress and egress logic blocks to support a different communication protocol. In response, the SoC can reconfigure the NoC such that the ingress and egress logic blocks support the new communication protocol used by the hardware elements. In this manner, the programmable NoC can support multiple communication protocols used to interface with other hardware elements in the SoC.

Abstract: A multi-chip structure that implements a configurable Network-on-Chip (NoC) for communication between chips is described herein. In an example, an apparatus includes a first chip comprising a first processing system and a first configurable NoC connected to the first processing system, and includes a second chip comprising a second processing system and a second configurable NoC connected to the second processing system. The first and second configurable NoCs are connected together via an external connector. The first and second processing systems are operable to obtain first and second information from off of the first and second chip and configure the first and second configurable NoCs based on the first and second information, respectively. The first and second processing systems are communicatively coupled with each other via the first and second configurable NoCs when the first and second configurable NoCs are configured based on the first and second information, respectively.

Abstract: A multi-chip structure that implements a configurable Network-on-Chip (NoC) for communication between chips is described herein. In an example, an apparatus includes a first chip comprising a first processing system and a first configurable NoC connected to the first processing system, and includes a second chip comprising a second processing system and a second configurable NoC connected to the second processing system. The first and second configurable NoCs are connected together via an external connector. The first and second processing systems are operable to obtain first and second information from off of the first and second chip and configure the first and second configurable NoCs based on the first and second information, respectively. The first and second processing systems are communicatively coupled with each other via the first and second configurable NoCs when the first and second configurable NoCs are configured based on the first and second information, respectively.

Abstract: A peripheral interconnect for configuring slave endpoint circuits, such as may be in a configurable network, in a system-on-chip (SoC) is described herein. In an example, an apparatus includes a processing system on a chip, a circuit block on the chip, and a configurable network on the chip. The processing system and the circuit block are connected to the configurable network. The configurable network includes a peripheral interconnect. The peripheral interconnect includes a root node and a plurality of switches. The root node and the plurality of switches are connected in a tree topology. First branches of the tree topology are connected to respective slave endpoint circuits of the configurable network. The slave endpoint circuits of the configurable network are programmable to configure the configurable network.

Abstract: Embodiments herein describe a SoC that includes a programmable NoC that can be reconfigured to support different interface communication protocols. In one embodiment, the NoC includes ingress and egress logic blocks which permit hardware elements in the SoC (e.g., processors, memory, programmable logic blocks, etc.) to transmit and receive data using the NoC. The ingress and egress logic blocks may first be configured to support a particular communication protocol for interfacing with the hardware elements. However, at a later time, the user may wish to reconfigure the ingress and egress logic blocks to support a different communication protocol. In response, the SoC can reconfigure the NoC such that the ingress and egress logic blocks support the new communication protocol used by the hardware elements. In this manner, the programmable NoC can support multiple communication protocols used to interface with other hardware elements in the SoC.

Abstract: Examples of the present disclosure generally relate to integrated circuits, such as a system-on-chip (SoC), that include a memory subsystem. In some examples, an integrated circuit includes a first master circuit in a first power domain on a chip; a second master circuit in a second power domain on the chip; and a first memory controller in a third power domain on the chip. The first master circuit and the second master circuit each are configured to access memory via the first memory controller. The first power domain and the second power domain each are separate and independent from the third power domain.

Abstract: An example method of generating a configuration for a network on chip (NoC) in a programmable device includes: receiving traffic flow requirements for a plurality of traffic flows; assigning routes through the NoC for each traffic flow based on the traffic flow requirements; determining arbitration settings for the traffic flows along the assigned routes; generating programming data for the NoC; and loading the programming data to the programmable device to configure the NoC.

Abstract: An example integrated circuit (IC) includes a network-on-chip (NoC), a master device coupled to the NoC, a memory controller coupled to the NoC configured to control a memory coupled to the IC, and an inline error-correcting code (ECC) circuit coupled to the NoC. The ECC circuit is configured to receive read and write transactions from the master device that target the memory, compute ECC data based on the read and write transactions, and provide outgoing transactions to the memory controller.

Abstract: An example integrated circuit (IC) includes a network-on-chip (NoC), a master device coupled to the NoC, a memory controller coupled to the NoC configured to control a memory coupled to the IC, and an inline error-correcting code (ECC) circuit coupled to the NoC. The ECC circuit is configured to receive read and write transactions from the master device that target the memory, compute ECC data based on the read and write transactions, and provide outgoing transactions to the memory controller.

Abstract: A disclosed network on chip includes a semiconductor die and switches disposed on the semiconductor die. Each switch has ports configured to receive packets from and transmit packets to at least two other switches. Each switch includes first circuitry that specifies a first mapping of interface identifiers of interfaces on the semiconductor die to port identifiers, and second circuitry that specifies a second mapping of region identifiers of regions of the semiconductor die to port identifiers. Each switch further includes third circuitry coupled to the first and second circuitry. The third circuitry is configured to select, in response to an input packet that specifies a destination region and a destination interface, a port based on the specification of the destination region, specification of the destination interface, first mapping, and second mapping, and output the packet on the selected port.