Patents by Inventor Ian McCallum
Ian McCallum has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11916780Abstract: A system and method to transmit frames from a first node to a second node over a plurality of radio links comprising a classifier to classify said frames according to one of a plurality of flow and a sequence number within said one of said plurality of flow and adding said flow and sequence number in a header of said classified frame a splitter receiving said classified frames from said classifier and distributing said classified frames on one of said plurality of radio links for transmission to said second node, a joiner receiving said classified frames and reordering them using an indexed sequence queue corresponding to each of said plurality of flows, a timer for waiting for frames missing in the sequence in one of said indexed sequence queue, wherein when said timer expires, if said frame has not arrived it is deemed lost and a forwarder to extract frames from said sequence queue to forward.Type: GrantFiled: November 28, 2022Date of Patent: February 27, 2024Assignee: Aviat U.S., Inc.Inventors: Ian McCallum, Bogdan Barna, Andrew Spurgeon
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Publication number: 20240049055Abstract: Disclosed are wireless communications systems including implementation of an adaptive distributed configuration of base stations. The base stations use an inter-base station protocol to exchange configuration data for use in configuring the base stations according to an identical solution independently determined by each of the base stations.Type: ApplicationFiled: August 4, 2023Publication date: February 8, 2024Inventors: Ian McCallum, Bradford Stimpson
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Patent number: 11749559Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.Type: GrantFiled: November 9, 2022Date of Patent: September 5, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Steven M. Shank, Anthony K. Stamper, Ian McCallum-Cook, Siva P. Adusumilli
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Publication number: 20230088112Abstract: A system and method to transmit frames from a first node to a second node over a plurality of radio links comprising a classifier to classify said frames according to one of a plurality of flow and a sequence number within said one of said plurality of flow and adding said flow and sequence number in a header of said classified frame a splitter receiving said classified frames from said classifier and distributing said classified frames on one of said plurality of radio links for transmission to said second node, a joiner receiving said classified frames and reordering them using an indexed sequence queue corresponding to each of said plurality of flows, a timer for waiting for frames missing in the sequence in one of said indexed sequence queue, wherein when said timer expires, if said frame has not arrived it is deemed lost and a forwarder to extract frames from said sequence queue to forward.Type: ApplicationFiled: November 28, 2022Publication date: March 23, 2023Inventors: Ian McCallum, Bogdan Barna, Andrew Spurgeon
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Publication number: 20230063731Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.Type: ApplicationFiled: November 9, 2022Publication date: March 2, 2023Inventors: Steven M. Shank, Anthony K. Stamper, Ian McCallum-Cook, Siva P. Adusumilli
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Patent number: 11558284Abstract: A system and method to transmit frames from a first node to a second node over a plurality of radio links comprising a classifier to classify said frames according to one of a plurality of flow and a sequence number within said one of said plurality of flow and adding said flow and sequence number in a header of said classified frame a splitter receiving said classified frames from said classifier and distributing said classified frames on one of said plurality of radio links for transmission to said second node, a joiner receiving said classified frames and reordering them using an indexed sequence queue corresponding to each of said plurality of flows, a timer for waiting for frames missing in the sequence in one of said indexed sequence queue, wherein when said timer expires, if said frame has not arrived it is deemed lost and a forwarder to extract frames from said sequence queue to forward.Type: GrantFiled: June 30, 2020Date of Patent: January 17, 2023Assignee: Redline Communications Inc.Inventors: Ian McCallum, Bogdan Barna, Andrew Spurgeon
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Publication number: 20220400450Abstract: A self-synchronization sensor system is provided. A self-synchronization sensor system for tracking fast moving assets comprising a plurality of beacons with known coordinates in a tunnel communicating with said plurality of beacons periodically during a synchronization interval and adjusting a beacon interval for each of said plurality of beacons such that one or more beacon messages are transmitted in short time intervals to the plurality of beacons in close proximity. The synchronization interval comprising a plurality of time slots, a first beacon from the plurality of beacons assigned a first time slot from the plurality of time slots within the synchronization interval and launches an origin and a progression of time slot allocation of the plurality of time slots from the origin based on the communication between the plurality of beacons.Type: ApplicationFiled: June 9, 2021Publication date: December 15, 2022Inventor: Ian McCALLUM
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Patent number: 11527432Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.Type: GrantFiled: November 2, 2020Date of Patent: December 13, 2022Assignee: GlobalFoundries U.S. Inc.Inventors: Steven M. Shank, Anthony K. Stamper, Ian McCallum-Cook, Siva P. Adusumilli
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Publication number: 20210409309Abstract: A system and method to transmit frames from a first node to a second node over a plurality of radio links comprising a classifier to classify said frames according to one of a plurality of flow and a sequence number within said one of said plurality of flow and adding said flow and sequence number in a header of said classified frame a splitter receiving said classified frames from said classifier and distributing said classified frames on one of said plurality of radio links for transmission to said second node, a joiner receiving said classified frames and reordering them using an indexed sequence queue corresponding to each of said plurality of flows, a timer for waiting for frames missing in the sequence in one of said indexed sequence queue, wherein when said timer expires, if said frame has not arrived it is deemed lost and a forwarder to extract frames from said sequence queue to forward.Type: ApplicationFiled: June 30, 2020Publication date: December 30, 2021Inventors: Ian McCallum, Bogdan Barna, Andrew Spurgeon
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Publication number: 20210367308Abstract: In accordance with at least selected embodiments, novel or improved porous membranes or substrates, separator membranes, separators, composites, electrochemical devices, batteries, methods of making such membranes or substrates, separators, and/or batteries, and/or methods of using such membranes or substrates, separators and/or batteries are disclosed. In accordance with at least certain embodiments, novel or improved microporous membranes, battery separator membranes, separators, energy storage devices, batteries including such separators, methods of making such membranes, separators, and/or batteries, and/or methods of using such membranes, separators and/or batteries are disclosed. In accordance with at least certain selected embodiments, a separator for a battery which has an oxidation protective and binder-free deposition layer which is stable up to 5.2 volts or more, for example, up to 7 volts, in a battery is disclosed.Type: ApplicationFiled: July 27, 2021Publication date: November 25, 2021Inventors: Lie Shi, C. Glen Wensley, Zhengming Zhang, Katharine Chemelewski, Junqing Ma, Ronnie E. Smith, Kwantai Cho, Weifeng Fang, Changqing Wang Adams, Ian McCallum, Jun Nada, Shante P. Williams, Jacob S. Mangum
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Patent number: 11158535Abstract: Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. Shallow trench isolation regions extend from a top surface of a semiconductor substrate into the semiconductor substrate. The semiconductor substrate contains single-crystal semiconductor material, and the shallow trench isolation regions are positioned to surround an active device region of the semiconductor substrate. A polycrystalline layer is formed in the semiconductor substrate. The polycrystalline layer has a first section beneath the active device region and a second section beneath the plurality of shallow trench isolation regions. The first section of the polycrystalline layer is located at a different depth relative to the top surface of the semiconductor substrate than the second section of the polycrystalline layer.Type: GrantFiled: October 10, 2019Date of Patent: October 26, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Steven M. Shank, Anthony K. Stamper, Siva P. Adusumilli, Ian McCallum-Cook, Michel J. Abou-Khalil
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Patent number: 11094995Abstract: In accordance with at least selected embodiments, novel or improved porous membranes or substrates, separator membranes, separators, composites, electrochemical devices, batteries, methods of making such membranes or substrates, separators, and/or batteries, and/or methods of using such membranes or substrates, separators and/or batteries are disclosed. In accordance with at least certain embodiments, novel or improved microporous membranes, battery separator membranes, separators, energy storage devices, batteries including such separators, methods of making such membranes, separators, and/or batteries, and/or methods of using such membranes, separators and/or batteries are disclosed. In accordance with at least certain selected embodiments, a separator for a battery which has an oxidation protective and binder-free deposition layer which is stable up to 5.2 volts or more, for example, up to 7 volts, in a battery is disclosed.Type: GrantFiled: July 22, 2016Date of Patent: August 17, 2021Assignee: Celgard, LLCInventors: Lie Shi, C. Glen Wensley, Zhengming Zhang, Katharine Chemelewski, Junqing Ma, Ronnie E. Smith, Kwantai Cho, Weifeng Fang, Changqing Wang Adams, Ian McCallum, Jun Nada, Shante P. Williams, Jacob S. Mangum
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Publication number: 20210111063Abstract: Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. Shallow trench isolation regions extend from a top surface of a semiconductor substrate into the semiconductor substrate. The semiconductor substrate contains single-crystal semiconductor material, and the shallow trench isolation regions are positioned to surround an active device region of the semiconductor substrate. A polycrystalline layer is formed in the semiconductor substrate. The polycrystalline layer has a first section beneath the active device region and a second section beneath the plurality of shallow trench isolation regions. The first section of the polycrystalline layer is located at a different depth relative to the top surface of the semiconductor substrate than the second section of the polycrystalline layer.Type: ApplicationFiled: October 10, 2019Publication date: April 15, 2021Inventors: Steven M. Shank, Anthony K. Stamper, Siva P. Adusumilli, Ian McCallum-Cook, Michel J. Abou-Khalil
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Publication number: 20210074577Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.Type: ApplicationFiled: November 2, 2020Publication date: March 11, 2021Inventors: Steven M. Shank, Anthony K. Stamper, Ian McCallum-Cook, Siva P. Adusumilli
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Patent number: 10832940Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.Type: GrantFiled: December 13, 2018Date of Patent: November 10, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Steven M. Shank, Anthony K. Stamper, Ian McCallum-Cook, Siva P. Adusumilli
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Publication number: 20200176589Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. A semiconductor layer is implanted over a first depth range of an inert gas species to modify the crystal structure of a semiconductor material of the semiconductor layer and form a first modified region. The semiconductor layer is annealed with a first annealing process to convert the semiconductor material within the first modified region to a non-single-crystal layer. The semiconductor layer is also implanted with ions of an element over a second depth range to modify the crystal structure of the semiconductor material of the semiconductor layer and form a second modified region containing a concentration of the element. The semiconductor layer is annealed with a second annealing process to convert the semiconductor material within the second modified region to an insulator layer containing the element.Type: ApplicationFiled: December 3, 2018Publication date: June 4, 2020Inventors: Siva P. Adusumilli, John J. Ellis-Monaghan, Anthony K. Stamper, Ian McCallum-Cook, Mark Goldstein
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Publication number: 20200161218Abstract: Through-substrate vias (TSVs) extend through a high resistivity semiconductor substrate laterally spaced and isolated from an active device formed over the substrate by deep trench isolation (DTI) structures. The deep trench isolation structures may extend partially or entirely through the substrate, and may include an air gap. The deep trench isolation structures entirely surround the active device and the TSVs.Type: ApplicationFiled: November 16, 2018Publication date: May 21, 2020Inventors: Steven SHANK, Ian MCCALLUM-COOK, John HALL
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Patent number: 10651281Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. A semiconductor layer is implanted over a first depth range of an inert gas species to modify the crystal structure of a semiconductor material of the semiconductor layer and form a first modified region. The semiconductor layer is annealed with a first annealing process to convert the semiconductor material within the first modified region to a non-single-crystal layer. The semiconductor layer is also implanted with ions of an element over a second depth range to modify the crystal structure of the semiconductor material of the semiconductor layer and form a second modified region containing a concentration of the element. The semiconductor layer is annealed with a second annealing process to convert the semiconductor material within the second modified region to an insulator layer containing the element.Type: GrantFiled: December 3, 2018Date of Patent: May 12, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Siva P. Adusumilli, John J. Ellis-Monaghan, Anthony K. Stamper, Ian McCallum-Cook, Mark Goldstein
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Patent number: 10643927Abstract: Through-substrate vias (TSVs) extend through a high resistivity semiconductor substrate laterally spaced and isolated from an active device formed over the substrate by deep trench isolation (DTI) structures. The deep trench isolation structures may extend partially or entirely through the substrate, and may include an air gap. The deep trench isolation structures entirely surround the active device and the TSVs.Type: GrantFiled: November 16, 2018Date of Patent: May 5, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Steven Shank, Ian McCallum-Cook, John Hall
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Publication number: 20190295881Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.Type: ApplicationFiled: December 13, 2018Publication date: September 26, 2019Inventors: Steven M. Shank, Anthony K. Stamper, Ian McCallum-Cook, Siva P. Adusumilli