Patents by Inventor Ian P. Shaeffer

Ian P. Shaeffer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11349478
    Abstract: In an integrated circuit component having a command interface to receive commands, a data interface to receive write data during a write-data reception interval, and first and second registers, control circuitry within the integrated circuit component responds to one or more of the commands by storing within the first register and the second register, respectively, a first control value that specifies a first termination to be applied to the data interface during the write-data reception interval, and a second control value that specifies a second termination to be applied to the data interface after the write-data reception interval transpires.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: May 31, 2022
    Assignee: Rambus Inc.
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Publication number: 20220147472
    Abstract: An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.
    Type: Application
    Filed: November 23, 2021
    Publication date: May 12, 2022
    Inventors: Ian P. Shaeffer, Arun Vaidyanath, Sanku Mukherjee
  • Patent number: 11302368
    Abstract: A memory device includes a first receive circuit to receive a control signal of a memory access request from a memory controller. A second receive circuit receives a timing signal from the memory controller. The memory device includes circuitry to transmit, during a calibration mode of operation, feedback to the memory controller along a data path, the feedback indicative of a phase relationship between the control signal and the timing signal.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: April 12, 2022
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • Publication number: 20220084571
    Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.
    Type: Application
    Filed: July 12, 2021
    Publication date: March 17, 2022
    Inventors: Bret Stott, Frederick A. Ware, Ian P. Shaeffer, Yuanlong Wang
  • Patent number: 11270741
    Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: March 8, 2022
    Assignee: Rambus Inc.
    Inventors: James E. Harris, Thomas Vogelsang, Frederick A. Ware, Ian P. Shaeffer
  • Publication number: 20220057845
    Abstract: A computing device can include an enclosure that defines an internal volume and an external surface. An input component can be positioned at the external surface. A processing unit and a memory can be communicatively coupled and disposed within the internal volume. A singular input/output port can be positioned at an orifice defined by the enclosure. The singular input/output port can be communicatively coupled to the processing unit and the memory. The singular input/output port can be configured to receive data and power and configured to output data from the processing unit. The computing device can include an air-moving apparatus to move air along an airflow pathway. The enclosure can include a thermally conductive base.
    Type: Application
    Filed: August 2, 2021
    Publication date: February 24, 2022
    Inventors: Michael E. Leclerc, Brett W. Degner, Ian P. Shaeffer
  • Patent number: 11200181
    Abstract: An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: December 14, 2021
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Arun Vaidyanath, Sanku Mukherjee
  • Publication number: 20210383740
    Abstract: An exemplary computer console can generate one or more video streams having image data relating to an image or a series of images, also referred to as video, to be presented by an electronic display device. The exemplary computer console can provide the one or more video streams to the electronic display device over one or more transport streams. The exemplary computer console can effectively throttle a video stream bitrate of the one or more video streams to be less than of the standard defined transport stream bitrate of the one or more transport streams to allow the transport of the one or more video streams over the one or more transport streams.
    Type: Application
    Filed: May 5, 2021
    Publication date: December 9, 2021
    Applicant: Apple Inc.
    Inventors: Reese A. SCHREIBER, Carlos M. CALDERON, Collin L. PIEPER, Ian P. SHAEFFER, Jeffrey R. WILCOX, Robert L. RIDENOUR
  • Patent number: 11188141
    Abstract: Circuits, methods, and apparatus that may determine one or more characteristics relating to a mains power supply received by a computer system, and may then determine a maximum amount of power that may be drawn by the computer system given the determined characteristics. An example may provide a computer system having a power supply circuit that may include a detection circuit to receive a mains power supply and to detect a characteristic of the mains power supply. In response to the detected characteristic, the detection circuit may provide an output to a circuit in the computer system that sets a limit on a current that may be drawn by the circuit. In this example, the characteristic may be an RMS value of the mains power supply waveform, a location of where the mains power supply is being received, a quality of the mains power supply, or other characteristic.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: November 30, 2021
    Assignee: Apple Inc.
    Inventors: Corey N. Axelowitz, William R. Allan, II, Eric C. Gaertner, Ian P. Shaeffer, Ronald P. Songco, John T. Orchard
  • Patent number: 11176280
    Abstract: Techniques are disclosed in which a secure circuit controls a gating circuit to enable or disable other circuity of a device (e.g., one or more input sensors). For example, the gating circuit may be a power gating circuit and the secure circuit may be configured to disable power to an input sensor in certain situations. As another example, the gating circuit may be a clock gating circuit and the secure circuit may be configured to disable the clock to an input sensor. As yet another example, the gating circuit may be configured to gate a control bus and the secure circuit may be configured to disable control signals to an input sensor. In some embodiments, hardware resources included in or controlled by the secure circuit are not accessible by other elements of the device, other than by sending requests to a predetermined set of memory locations (e.g., a secure mailbox).
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: November 16, 2021
    Assignee: Apple Inc.
    Inventors: Pierre-Olivier J. Martel, Jeffrey R. Wilcox, Ian P. Shaeffer, Andrew D. Myrick, Robert W. Hill, Tristan F. Schaap
  • Patent number: 11062748
    Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: July 13, 2021
    Assignee: RAMBUS INC.
    Inventors: Bret Stott, Frederick A. Ware, Ian P. Shaeffer, Yuanlong Wang
  • Publication number: 20210193197
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Application
    Filed: November 19, 2020
    Publication date: June 24, 2021
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • Publication number: 20210098033
    Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.
    Type: Application
    Filed: October 7, 2020
    Publication date: April 1, 2021
    Inventors: James E. Harris, Thomas Vogelsang, Frederick A. Ware, Ian P. Shaeffer
  • Publication number: 20210098280
    Abstract: This application is directed to a system including a plurality of devices that are stacked one on top of another. Each device includes a substrate having two opposing surfaces. A first row of contacts is coupled on a first surface and includes a first contact and a second contact that are adjacent to each other. A second row of contacts is coupled on a respective second surface and includes a third contact. Each contact in the second row of contacts is physically aligned with an opposite contact in the first row. The third contact is disposed opposite and physically aligned with the first contact in the first row, and electrically coupled to the second contact in the first row. Operational circuitry is electrically coupled to at least the first contact on the first row, and at least two of the plurality of devices have distinct operational circuitry.
    Type: Application
    Filed: October 12, 2020
    Publication date: April 1, 2021
    Inventors: Frederick A. Ware, Ely K. Tsern, Ian P. Shaeffer
  • Patent number: 10944400
    Abstract: A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: March 9, 2021
    Assignee: Rambus Inc.
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Publication number: 20210049118
    Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.
    Type: Application
    Filed: July 6, 2020
    Publication date: February 18, 2021
    Inventors: Jared L. Zerbe, Ian P. Shaeffer, John Eble
  • Patent number: 10902891
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: January 26, 2021
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • Publication number: 20200358441
    Abstract: In an integrated circuit component having a command interface to receive commands, a data interface to receive write data during a write-data reception interval, and first and second registers, control circuitry within the integrated circuit component responds to one or more of the commands by storing within the first register and the second register, respectively, a first control value that specifies a first termination to be applied to the data interface during the write-data reception interval, and a second control value that specifies a second termination to be applied to the data interface after the write-data reception interval transpires.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Patent number: 10811062
    Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: October 20, 2020
    Assignee: Rambus Inc.
    Inventors: James E. Harris, Thomas Vogelsang, Frederick A. Ware, Ian P. Shaeffer
  • Patent number: 10804139
    Abstract: This application is directed to a system including a plurality of devices that are stacked one on top of another. Each device includes a substrate having two opposing surfaces. A first row of contacts is coupled on a first surface and includes a first contact and a second contact that are adjacent to each other. A second row of contacts is coupled on a respective second surface and includes a third contact. Each contact in the second row of contacts is physically aligned with an opposite contact in the first row. The third contact is disposed opposite and physically aligned with the first contact in the first row, and electrically coupled to the second contact in the first row. Operational circuitry is electrically coupled to at least the first contact on the first row, and at least two of the plurality of devices have distinct operational circuitry.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: October 13, 2020
    Assignee: RAMBUS INC.
    Inventors: Frederick A. Ware, Ely K. Tsern, Ian P. Shaeffer