Patents by Inventor Ian P. Shaeffer

Ian P. Shaeffer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory controller with staggered request signal output
    Patent number: 9691447
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: June 27, 2017
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • MEMORY WITH DEFERRED FRACTIONAL ROW ACTIVATION
    Publication number: 20170178702
    Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.
    Type: Application
    Filed: December 26, 2016
    Publication date: June 22, 2017
    Inventors: James E. Harris, Thomas Vogelsang, Frederick A. Ware, Ian P. Shaeffer
  • On-die termination control
    Patent number: 9660648
    Abstract: A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: May 23, 2017
    Assignee: Rambus Inc.
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Error correction in a memory device
    Patent number: 9575835
    Abstract: A dynamic random access memory (DRAM) array is configured for selective repair and error correction of a subset of the array. Error-correcting code (ECC) is provided to a selected subset of the array to protect a row or partial row of memory cells where one or more weak memory cells are detected. By adding a sense amplifier stripe to the edge of the memory array, the adjacent edge segment of the array is employed to store ECC information associated with the protected subsets of the array. Bit replacement is also applied to defective memory cells. By implementing ECC selectively rather than to the entire array, integrity of the memory array is maintained at minimal cost to the array in terms of area and energy consumption.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: February 21, 2017
    Assignee: Rambus Inc.
    Inventors: Thomas Vogelsang, Suresh N. Rajan, Ian P. Shaeffer, Frederick A. Ware, Wayne F. Ellis
  • Memory with deferred fractional row activation
    Patent number: 9570126
    Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: February 14, 2017
    Assignee: Rambus Inc.
    Inventors: James E. Harris, Thomas Vogelsang, Frederick A. Ware, Ian P. Shaeffer
  • Clock generation for timing communications with ranks of memory devices
    Patent number: 9563228
    Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: February 7, 2017
    Assignee: RAMBUS INC.
    Inventors: Jared L. Zerbe, Ian P. Shaeffer, John Eble
  • MEMORY CONTROLLER WITH PHASE ADJUSTED CLOCK FOR PERFORMING MEMORY OPERATIONS
    Publication number: 20160343417
    Abstract: In an illustrative embodiment, the memory circuit includes first and second data paths on which data is transferred for read and write memory operations and first and second mixer circuits for adjusting the phase of clock signals applied to their inputs. The mixer circuits are cross-coupled so that the outputs of the first and second mixers are both available to both the first and second data paths. One mixer is used to provide a first phase adjusted clock signal for use by the operating circuit and the other mixer is used to provide a second phase adjusted clock signal for use by a following operation whatever that may be.
    Type: Application
    Filed: May 20, 2016
    Publication date: November 24, 2016
    Inventors: Ian P. Shaeffer, Lei Luo
  • MEMORY WITH DEFERRED FRACTIONAL ROW ACTIVATION
    Publication number: 20160307609
    Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.
    Type: Application
    Filed: April 26, 2016
    Publication date: October 20, 2016
    Inventors: James E. Harris, Thomas Vogelsang, Frederick A. Ware, Ian P. Shaeffer
  • Strobe Acquisition and Tracking
    Publication number: 20160232953
    Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.
    Type: Application
    Filed: February 5, 2016
    Publication date: August 11, 2016
    Inventors: Bret Stott, Frederick A. Ware, Ian P. Shaeffer, Yuanlong Wang
  • ON-DIE TERMINATION CONTROL
    Publication number: 20160233863
    Abstract: A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs.
    Type: Application
    Filed: April 19, 2016
    Publication date: August 11, 2016
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Memory controller with phase adjusted clock for performing memory operations
    Patent number: 9378786
    Abstract: In an illustrative embodiment, the memory circuit includes first and second data paths on which data is transferred for read and write memory operations and first and second mixer circuits for adjusting the phase of clock signals applied to their inputs. The mixer circuits are cross-coupled so that the outputs of the first and second mixers are both available to both the first and second data paths. One mixer is used to provide a first phase adjusted clock signal for use by the operating circuit and the other mixer is used to provide a second phase adjusted clock signal for use by a following operation whatever that may be.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: June 28, 2016
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Lei Luo
  • Controlling a flash device having time-multiplexed, on-die-terminated signaling interface
    Patent number: 9337835
    Abstract: An IC die transmits command signals, address signals and data signals to a flash memory device at respective times via a time-multiplexed external signaling line, the data signals representing data to be stored within an array of non-volatile storage elements of the flash memory device. The IC die additionally transmits a control signal to the flash memory device via one or more external control signal lines, the control signal directing the flash memory device to switchably couple an on-die termination element to the time-multiplexed signaling line.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: May 10, 2016
    Assignee: Rambus Inc.
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • DISAGGREGATED MEMORY APPLIANCE
    Publication number: 20160124872
    Abstract: Exemplary embodiments provide a disaggregated memory appliance, comprising: a plurality of leaf memory switches that manage one or more memory channels of one or more of leaf memory modules; a low-latency memory switch that arbitrarily connects one or more external processors to the plurality of leaf memory modules over a host link; and a low-latency routing protocol used by both the low-latency memory switch and the leaf memory switches that encapsulates memory technology specific semantics by use of tags that uniquely identify specific types of memory technology used in the memory appliance during provisioning, monitoring and operation.
    Type: Application
    Filed: September 28, 2015
    Publication date: May 5, 2016
    Inventors: Steven L. Shrader, Harry R. Rogers, Robert Brennan, Ian P. Shaeffer
  • Memory with deferred fractional row activation
    Patent number: 9330735
    Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the sub-row to be activated.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: May 3, 2016
    Assignee: Rambus Inc.
    Inventors: James Edward Harris, Thomas Vogelsang, Frederick A. Ware, Ian P. Shaeffer
  • DISAGGREGATED MEMORY APPLIANCE
    Publication number: 20160117129
    Abstract: Example embodiments provide a disaggregated memory appliance, comprising: a plurality of leaf memory switches that manage one or more memory channels of one or more of leaf memory modules; a low-latency memory switch that arbitrarily connects one or more external processors to the plurality of leaf memory modules over a host link; and a management processor that responds to requests from one or more external processors for management, maintenance, configuration and provisioning of the leaf memory modules within the memory appliance.
    Type: Application
    Filed: September 28, 2015
    Publication date: April 28, 2016
    Inventors: Steven L. Shrader, Harry R. Rogers, Robert Brennan, Ian P. Shaeffer
  • Clock Generation for Timing Communications with Ranks of Memory Devices
    Publication number: 20160116938
    Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.
    Type: Application
    Filed: November 30, 2015
    Publication date: April 28, 2016
    Inventors: Jared L. Zerbe, Ian P. Shaeffer, John Eble
  • Controlling on-die termination in a nonvolatile memory
    Patent number: 9306568
    Abstract: A memory controller transmits a plurality of control values to a non-volatile memory device together with one or more programming commands. The plurality of control values include (i) a first control value that specifies a first termination resistance to be applied to an I/O node of the non-volatile memory device during an interval in which a first data signal transmitted on a bidirectional signaling line coupled to the I/O node is to be received within the non-volatile memory device and (ii) a second control value that specifies a second termination resistance to be applied to the I/O node during an interval in which a second data signal is transmitted on the bidirectional signaling line by another non-volatile memory device.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: April 5, 2016
    Assignee: Rambus Inc.
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Nonvolatile memory with chip-select/device-address triggered on-die termination
    Patent number: 9306565
    Abstract: A non-volatile memory device determines, based at least partly on a first multi-bit device address received via a signaling interface and an incoming chip-select signal, whether the device is to participate in a memory access transaction by receiving or outputting data via an I/O node of the signaling interface. Based at least in part on that determination, on-die termination circuitry within the non-volatile memory device switchably couples or decouples a termination resistance between the I/O node and a supply voltage node during a data transmission phase of the memory access transaction.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: April 5, 2016
    Assignee: Rambus Inc.
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Nonvolatile memory with command-driven on-die termination
    Patent number: 9306566
    Abstract: On-die termination circuitry within a non-volatile memory device applies a first termination resistance to an I/O node in response to a data storage command indicating that a data signal conveyed on a bidirectional signaling line is to be received within the non-volatile memory device via the I/O node, and applies a second termination resistance to the I/O node in response to information indicating that another memory device is to output a data signal onto the bidirectional signaling line.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: April 5, 2016
    Assignee: Rambus Inc.
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Nonvolatile memory device with on-die control and data signal termination
    Patent number: 9306564
    Abstract: In a non-volatile memory device having an array of non-volatile storage elements, control information received via one or more control input nodes indicates, at different times, that (i) data signals representative of data to be stored within the array of non-volatile storage elements are to be received via a plurality of input/output (I/O) nodes of the non-volatile memory device, and (ii) data signals representative of data read from the array of non-volatile storage elements are to be output via the plurality of I/O nodes. First termination elements are switchably coupled to and decoupled from the I/O nodes based at least in part on the control information, and second termination elements are switchably coupled to and decoupled from the one or more control input nodes based at least in part on the control information.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: April 5, 2016
    Assignee: Rambus Inc.
    Inventors: Kyung Suk Oh, Ian P. Shaeffer