Abstract: A graphics processing system comprises a pair of graphics processing units that are connected to each other via communications bridges that can allow communication between the connected graphics processing units. One of the graphics processing units is operable to act as a master graphics processing unit controlling graphics processing operations on the other graphics processing unit which is operable as a slave graphics processing unit to perform graphics processing operations under the control of the master graphics processing unit. Each graphics processing unit of the pair of graphics processing units is also capable of operating in a standalone mode, in which the graphics processing unit operates independently of the other graphics processing unit to perform a graphics processing task.

Abstract: A data processing system includes a processing pipeline for the parallel execution of a plurality of threads. An issue controller issues threads to the processing pipeline. A stall manager controls the stalling and unstalling of threads when a cache miss occurs within a cache memory. The issue controller issues the threads to the processing pipeline in accordance with both a main sequence and a pilot sequence. The pilot sequence is followed such that threads within the pilot sequence are issued at least a given time ahead of their neighbors within a main sequence. The given time corresponds approximately to the latency associated with a cache miss. The threads may be arranged in groups corresponding to blocks of pixels for processing within a graphics processing unit.

Abstract: A graphics processing apparatus and method of graphics processing is disclosed. Obscuration identification circuitry is configured to receive graphics fragments from rasterization circuitry and to identify an obscuration condition if a received graphics fragment, in combination with at least one previously received graphics fragment, will obscure at least one further previously received graphics fragment. Process killing circuitry is configured to prevent further processing occurring in the graphics processing apparatus with respect to the at least one further previously received graphics fragment if the obscuration identification circuitry identifies the obscuration condition.

Abstract: A processing apparatus comprising: several processors for processing data; a hierarchical memory system comprising a memory accessible to all the processors, and several caches corresponding to each of the processors, each of the caches being accessible to the corresponding processor and comprising storage locations and corresponding indicators. There is also cache coherency control circuitry for maintaining coherency of data stored in the hierarchical memory system. The processors are configured to respond to receipt of a predefined request to perform an operation on a data item to determine if the cache corresponding to the processor receiving the request has a storage location allocated to the data item. If not, the processing apparatus is configured to: allocate a storage location within the cache to the data item, set the indicator corresponding to the storage location to indicate that the storage location is storing a delta value, set data in the allocated storage location to an initial value.

Abstract: A data processing system includes a processing pipeline for the parallel execution of a plurality of threads. An issue controller issues threads to the processing pipeline. A stall manager controls the stalling and unstalling of threads when a cache miss occurs within a cache memory. The issue controller issues the threads to the processing pipeline in accordance with both a main sequence and a pilot sequence. The pilot sequence is followed such that threads within the pilot sequence are issued at least a given time ahead of their neighbours within a main sequence. The given time corresponds approximately to the latency associated with a cache miss. The threads may be arranged in groups corresponding to blocks of pixels for processing within a graphics processing unit.

Abstract: A graphics processing apparatus and method of graphics processing is disclosed. Obscuration identification circuitry is configured to receive graphics fragments from rasterization circuitry and to identify an obscuration condition if a received graphics fragment, in combination with at least one previously received graphics fragment, will obscure at least one further previously received graphics fragment. Process killing circuitry is configured to prevent further processing occurring in the graphics processing apparatus with respect to the at least one further previously received graphics fragment if the obscuration identification circuitry identifies the obscuration condition.

Abstract: A processing apparatus comprising: several processors for processing data; a hierarchical memory system comprising a memory accessible to all the processors, and several caches corresponding to each of the processors, each of the caches being accessible to the corresponding processor and comprising storage locations and corresponding indicators. There is also cache coherency control circuitry for maintaining coherency of data stored in the hierarchical memory system. The processors are configured to respond to receipt of a predefined request to perform an operation on a data item to determine if the cache corresponding to the processor receiving the request has a storage location allocated to the data item. If not, the processing apparatus is configured to: allocate a storage location within the cache to the data item, set the indicator corresponding to the storage location to indicate that the storage location is storing a delta value, set data in the allocated storage location to an initial value.

Abstract: A windowing display using deferred drawing commands operates by processing the drawing commands that write to a tile 22 of a frame buffer 30 to form one or more new pixel values are stored within a tile memory 40. Dirty pixel data indicative of which pixels within the tile memory are dirty pixels storing new pixel values and which pixels within the tile memory are clean pixels not storing new pixel values is also formed. In dependence upon the dirty pixel data, the new pixel value stored within the tile memory are written to the frame buffer memory. Pixels stored within the frame buffer memory corresponding to clean pixels within the tile memory remain unaltered as they are not written.

Abstract: A windowing display using deferred drawing commands operates by processing the drawing commands that write to a tile 22 of a frame buffer 30 to form one or more new pixel values are stored within a tile memory 40. Dirty pixel data indicative of which pixels within the tile memory are dirty pixels storing new pixel values and which pixels within the tile memory are clean pixels not storing new pixel values is also formed. In dependence upon the dirty pixel data, the new pixel value stored within the tile memory are written to the frame buffer memory. Pixels stored within the frame buffer memory corresponding to clean pixels within the tile memory remain unaltered as they are not written.

Abstract: The technology described provides a technique for synchronization between pipelines in a data processing apparatus. The data processing apparatus comprises a main processor operable to execute a sequence of instructions, the main processor comprising a first pipeline having a first plurality of pipeline stages, and a coprocessor operable to execute coprocessor instructions in said sequence of instructions. The coprocessor comprises a second pipeline having a second plurality of pipeline stages, and each coprocessor instruction is arranged to be routed through both the first pipeline and the second pipeline.

Abstract: A data processing system is provided with a bus having separate write channels W and read channels R via which bus transactions are made. Bus transaction buffers 34 are provided within the bus structure to buffer write requests, particularly so as to alleviate problems associated with relatively slow bus slaves. The bus transaction buffers 34 are responsive to the memory addresses associated with write requests and read requests which pass through them to identify those to the same memory address, or memory addresses within a predetermined range, so as to either ensure a strict correct ordering of those transactions, read to follow write, or to satisfy a read following a write with a buffered write data value and then flushing the read request such that it does not reach its final destination.

Abstract: The present invention provides an apparatus and method for synchronizing a first pipeline and a second pipeline of a processor arranged to execute a sequence of instructions. The processor is arranged to route an instruction in the sequence through either the first or the second pipeline dependent on predetermined criteria, each pipeline having a plurality of pipeline stages including a retirement stage. Counter logic is provided for maintaining a first counter relating to the first pipeline and a second counter relating to the second pipeline. For each instruction in the first pipeline a determination is made as to when that instruction reaches a point within the first pipeline where an exception status of that instruction is resolved, and the counter logic is arranged to increment the first counter responsive to such determination.

Abstract: The present invention provides an apparatus and method for facilitating debugging of sequences of processing instructions. The apparatus comprises a processing circuit for executing processing instructions, the processing circuit having multiple states of operation, with each state of operation being assigned a context identifier to identify the state of operation. Further, logic is provided for facilitating debugging of sequences of processing instructions executed by the processing circuit. The logic comprises control logic, responsive to control parameters, to perform predetermined actions to facilitate debugging, and triggering logic for generating the control parameters dependent on data received from the processing circuit indicative of the processing being performed by the processing circuit.

Abstract: The present invention provides a data processing apparatus and method for evaluating condition codes comprising a pipelined processor operable to execute a sequence of instructions, a set of condition codes being maintained by the processor, and the state of the condition codes being set by execution of condition code setting instructions in the sequence. The sequence of instructions further includes conditional instructions that are conditionally executed depending on the state of a number of those condition codes, with the pipelined processor comprising a plurality of pipeline stages including a predetermined pipeline stage at which the state of the condition codes are set by the condition code setting instructions.

Abstract: The present invention relates to the management of caches in a data processing apparatus, and in particular to the management of caches of the type where data in the cache may be designated as locked to prevent that data from being overwritten. The data processing apparatus comprises a processor, an n-way set associative cache having a plurality of entries, each entry being arranged to store one or more data values and a corresponding address identifier, the processor being operable to select one or more of the n-ways to operate in a lockdown mode, the lockdown mode being used to lock data values into the corresponding way, and a plurality of lockdown controllers. Each lockdown controller is associated with a corresponding way and comprises an address register arranged to store an address range specified by the processor such that, when the corresponding way is in the lockdown mode, only data values whose address identifiers are within the address range are locked into the corresponding way.

Abstract: A translation lookaside buffer mechanism is described incorporating a set associative translation lookaside buffer operating in parallel with a fully associative translation lookaside buffer. Lockdown entries are stored within the fully associative translation lookaside buffer and non-lockdown entries are stored within the set associative translation lookaside buffer. Victim selection for the fully associative translation lookaside buffer 18 is performed using a control register within a coprocessor which is set under operating system software control.

Abstract: The present invention provides a data processing apparatus and method for saving return state. The data processing apparatus comprises a processing unit for executing data processing instructions, the processing unit having a plurality of modes of operation, with each mode of operation having a corresponding stack for storing data associated with that mode. The processing unit is responsive to a return state data processing instruction to write return state data of the processing unit from its current mode of operation to a stack corresponding to a different mode of operation to the current mode of operation. This approach significantly reduces code size and improves interrupt latency over known prior art techniques.

Abstract: The present invention provides an apparatus and method for synchronizing a first pipeline and a second pipeline of a processor arranged to execute a sequence of instructions. The processor is arranged to route an instruction in the sequence through either the first or the second pipeline dependent on predetermined criteria, each pipeline having a plurality of pipeline stages including a retirement stage. Counter logic is provided for maintaining a first counter relating to the first pipeline and a second counter relating to the second pipeline. For each instruction in the first pipeline a determination is made as to when that instruction reaches a point within the first pipeline where an exception status of that instruction is resolved, and the counter logic is arranged to increment the first counter responsive to such determination.

Abstract: The present invention provides a technique for synchronisation between pipelines in a data processing apparatus. The data processing apparatus comprises a main processor operable to execute a sequence of instructions, the main processor comprising a first pipeline having a first plurality of pipeline stages, and a coprocessor operable to execute coprocessor instructions in said sequence of instructions. The coprocessor comprises a second pipeline having a second plurality of pipeline stages, and each coprocessor instruction is arranged to be routed through both the first pipeline and the second pipeline.

Abstract: The present invention provides a data processing apparatus and method for evaluating condition codes. The data processing apparatus comprises a pipelined processor operable to execute a sequence of instructions, a set of condition codes being maintained by the processor, and the state of the condition codes being set by execution of condition code setting instructions in the sequence. The sequence of instructions further includes conditional instructions that are conditionally executed depending on the state of a number of those condition codes, with the pipelined processor comprising a plurality of pipeline stages including a predetermined pipeline stage at which the state of the condition codes are set by the condition code setting instructions.