Abstract: The present invention relates to the management of caches in a data processing apparatus, and in particular to the management of caches of the type where data in the cache may be designated as locked to prevent that data from being overwritten. The data processing apparatus comprises a processor, an n-way set associative cache having a plurality of entries, each entry being arranged to store one or more data values and a corresponding address identifier, the processor being operable to select one or more of the n-ways to operate in a lockdown mode, the lockdown mode being used to lock data values into the corresponding way, and a plurality of lockdown controllers. Each lockdown controller is associated with a corresponding way and comprises an address register arranged to store an address range specified by the processor such that, when the corresponding way is in the lockdown mode, only data values whose address identifiers are within the address range are locked into the corresponding way.

Abstract: The present invention provides a technique for operating an integrated circuit comprising a plurality of circuit elements, with a plurality of serial test scan chains, each being coupled to a different one of the circuit elements. A scan chain selector is responsive to a specified scan chain specifying value to select a corresponding one of the plurality of test scan chains. A scan chain controller is also provided which has a serial interface for receiving signals from outside of the integrated circuit, the scan chain controller comprising an instruction decoder for decoding scan chain controller instructions received from the serial interface. In accordance with the present invention, the decoder is responsive to a first scan chain controller instruction to specify a pre-determined scan chain specifying value and a second scan chain controller instruction for decoding by the decoder.

Abstract: A translation lookaside buffer mechanism 10 is described incorporating a set associative translation lookaside buffer 16 operating in parallel with a fully associative translation lookaside buffer 18. Lockdown entries are stored within the fully associative translation lookaside buffer 18 and non-lockdown entries are stored within the set associative translation lookaside buffer 16. Victim selection for the fully associative translation lookaside buffer 18 is performed using a control register 50 within a coprocessor 12 which is set under operating system software control.

Abstract: The present invention relates to the management of caches in a data processing apparatus, and in particular to the management of caches of the type where data in the cache may be designated as locked to prevent that data from being overwritten. The data processing apparatus comprises a processor, an n-way set associative cache having a plurality of entries, each entry being arranged to store one or more data values and a corresponding address identifier, the processor being operable to select one or more of the n-ways to operate in a lockdown mode, the lockdown mode being used to lock data values into the corresponding way, and a plurality of lockdown controllers. Each lockdown controller is associated with a corresponding way and comprises an address register arranged to store an address range specified by the processor such that, when the corresponding way is in the lockdown mode, only data values whose address identifiers are within the address range are locked into the corresponding way.

Abstract: The present invention provides an apparatus and method for facilitating debugging of sequences of processing instructions. The apparatus comprises a processing circuit for executing processing instructions, the processing circuit having multiple states of operation, with each state of operation being assigned a context identifier to identify the state of operation. Further, logic is provided for facilitating debugging of sequences of processing instructions executed by the processing circuit. The logic comprises control logic, responsive to control parameters, to perform predetermined actions to facilitate debugging, and triggering logic for generating the control parameters dependent on data received from the processing circuit indicative of the processing being performed by the processing circuit.

Abstract: The present invention provides a technique for operating an integrated circuit comprising a plurality of circuit elements, with a plurality of serial test scan chains, each being coupled to a different one of the circuit elements. A scan chain selector is responsive to a specified scan chain specifying value to select a corresponding one of the plurality of test scan chains. A scan chain controller is also provided which has a serial interface for receiving signals from outside of the integrated circuit, the scan chain controller comprising an instruction decoder for decoding scan chain controller instructions received from the serial interface. In accordance with the present invention, the decoder is responsive to a first scan chain controller instruction to specify a pre-determined scan chain specifying value and a second scan chain controller instruction for decoding by the decoder.

Abstract: The present invention provides a data processing apparatus and method for saving return state. The data processing apparatus comprises a processing unit for executing data processing instructions, the processing unit having a plurality of modes of operation, with each mode of operation having a corresponding stack for storing data associated with that mode. The processing unit is responsive to a return state data processing instruction to write return state data of the processing unit from its current mode of operation to a stack corresponding to a different mode of operation to the current mode of operation. This approach significantly reduces code size and improves interrupt latency over known prior art techniques.

Abstract: The present invention relates to the management of caches in a data processing apparatus, and in particular to the management of caches of the type where data in the cache may be designated as locked to prevent that data from being overwritten. The data processing apparatus comprises a processor, an n-way set associative cache having a plurality of entries, each entry being arranged to store one or more data values and a corresponding address identifier, the processor being operable to select one or more of the n-ways to operate in a lockdown mode, the lockdown mode being used to lock data values into the corresponding way, and a plurality of lockdown controllers. Each lockdown controller is associated with a corresponding way and comprises an address register arranged to store an address range specified by the processor such that, when the corresponding way is in the lockdown mode, only data values whose address identifiers are within the address range are locked into the corresponding way.

Abstract: A data processing system comprising a first circuit block 6 and a second circuit block 8 linked via an asynchronous first-in-first-out buffer circuit 12 is provided with a burst marker that identifies the first word in a burst transfer or an empty stage. The second circuit block 8 uses the burst marker to identify the last data word in a burst as being that word which immediately precedes such a burst marker.

Abstract: The present invention provides a data processing apparatus for fetching an instruction in to an instruction cache, comprising an instruction cache for storing instructions, and a processor core for outputting an instruction address to the instruction cache on an instruction address bus, and for receiving the instruction corresponding to that instruction address on an instruction data bus The processor core is arranged to issue a predetermined control signal to the instruction cache when outputting the instruction address to cause the instruction cache to perform an instruction fetch procedure.