Patents by Inventor Ian Young

Ian Young has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Magnetic and spin logic devices based on Jahn-Teller materials
    Patent number: 10910556
    Abstract: Described is an apparatus which comprises: a heat spreading layer; a first transition metal layer adjacent to the heat spreading layer; and a magnetic recording layer adjacent to the first transition metal layer. Described is an apparatus which comprises: a first electrode; a magnetic junction having a free magnet; and one or more layers of Jahn-Teller material adjacent to the first electrode and the free magnet of the magnetic junction.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Ian A. Young, Dmitri E. Nikonov, Ravi Pillarisetty, Uygar E. Avci
  • Configurable interconnect apparatus and method
    Patent number: 10901486
    Abstract: Described is an apparatus which comprises: a first electrical path comprising at least one driver and receiver; and a second electrical path comprising at least one driver and receiver, wherein the first and second electrical paths are to receive a same input signal, wherein the first electrical path and the second electrical path are parallel to one another and have substantially the same propagation delays, and wherein the second electrical path is enabled during a first operation mode and disabled during a second operation mode.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: January 26, 2021
    Assignee: Intel Corporation
    Inventors: Kaushik Vaidyanathan, Daniel H. Morris, Uygar E. Avci, Ian A. Young, Tanay Karnik, Huichu Liu
  • POLARIZATION GATE STACK SRAM
    Publication number: 20210020233
    Abstract: One embodiment provides an apparatus. The apparatus includes a first inverter comprising a first pull up transistor and a first pull down transistor; a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor; a first access transistor coupled to the first inverter; and a second access transistor coupled to the second inverter. A gate electrode of one transistor of each inverter comprises a polarization layer.
    Type: Application
    Filed: October 1, 2020
    Publication date: January 21, 2021
    Inventors: Daniel H. MORRIS, Uygar E. AVCI, Ian A. YOUNG
  • Vertical memory control circuitry located in interconnect layers
    Patent number: 10886286
    Abstract: An embodiment includes a substrate having a surface; a first layer that includes a metal and is on the substrate; a second layer that includes the metal and is on the first layer; a first switching device between the first and second layers; a second switching device between the first and second layers; a capacitor between the first and second layers, the capacitor including ferroelectric materials; a memory cell that includes the first switching device and the capacitor; an interconnect line that couples the first and second switching devices to each other; wherein: (a) the surface is substantially disposed in a first plane, and (b) a second plane is parallel to the first plane, the second plane intersecting the first and second switching devices. Other embodiments are addressed herein.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Ashish Verma Penumatcha, Daniel H. Morris, Uygar E. Avci, Ian A. Young
  • Pipeline circuit architecture to provide in-memory computation functionality
    Patent number: 10884957
    Abstract: Techniques and mechanisms for performing in-memory computations with circuitry having a pipeline architecture. In an embodiment, various stages of a pipeline each include a respective input interface and a respective output interface, distinct from said input interface, to couple to different respective circuitry. These stages each further include a respective array of memory cells and circuitry to perform operations based on data stored by said array. A result of one such in-memory computation may be communicated from one pipeline stage to a respective next pipeline stage for use in further in-memory computations. Control circuitry, interconnect circuitry, configuration circuitry or other logic of the pipeline precludes operation of the pipeline as a monolithic, general-purpose memory device. In other embodiments, stages of the pipeline each provide a different respective layer of a neural network.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Amrita Mathuriya, Sasikanth Manipatruni, Victor W. Lee, Abhishek Sharma, Huseyin E. Sumbul, Gregory Chen, Raghavan Kumar, Phil Knag, Ram Krishnamurthy, Ian Young
  • Ferroelectric memory-based synapses
    Patent number: 10885963
    Abstract: An embodiment includes an apparatus comprising: a first layer and a second layer; a first gate including first gate portions and a second gate including second gate portions; wherein the first layer: (a) is monolithic, (b) is between the first gate portions and is also between the second gate portions, and (c) includes a semiconductor material; wherein the second layer: (a) is between the first layer and at least one of the first gate portions and is also between the first layer and at least one of the second gate portions, and (b) includes oxygen and at least one of hafnium, silicon, yttrium, zirconium, barium, titanium, lead, or combinations thereof; wherein (a) a first plane intersects the first gate portions and the first and second layers, and (b) a second plane intersects the second gate portions and the first and second layers. Other embodiments are described herein.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Dmitri Nikonov, Ilya Karpov, Ian Young
  • Integrated circuit device with a two-dimensional semiconductor material and a dielectric material that includes fixed charges
    Patent number: 10886265
    Abstract: An embodiment includes an apparatus comprising: a dielectric material including fixed charges, the fixed charges each having a first polarity; a channel comprising a channel material, the channel material including a 2-dimensional (2D) material; a drain node; and a source node including a source material, the source material including at least one of the 2D material and an additional 2D material; wherein the source material: (a) includes charges each having a second polarity that is opposite the first polarity, (b) directly contacts the dielectric material. Other embodiments are described herein.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Ashish Verma Penumatcha, Uygar Avci, Ian Young
  • STAGGERED LINES FOR INTERCONNECT PERFORMANCE IMPROVEMENT AND PROCESSES FOR FORMING SUCH
    Publication number: 20200411427
    Abstract: An interconnect structure is disclosed. The interconnect structure includes a first line of interconnects and a second line of interconnects. The first line of interconnects and the second line of interconnects are staggered. The individual interconnects of the second line of interconnects are laterally offset from individual interconnects of the first line of interconnects. A dielectric material is adjacent to at least a portion of the individual interconnects of at least one of the first line of interconnects and the second line of interconnects.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Kevin Lai LIN, Manish CHANDHOK, Miriam RESHOTKO, Christopher JEZEWSKI, Eungnak HAN, Gurpreet SINGH, Sarah ATANASOV, Ian A. YOUNG
  • MACRO STORAGE CELL COMPOSED OF MULTIPLE STORAGE DEVICES EACH CAPABLE OF STORING MORE THAN TWO STATES
    Publication number: 20200411088
    Abstract: An apparatus. The apparatus includes a macro storage cell having a first storage device and a second storage device. The first and second storage devices each able to store more than two states. The macro storage cell to store multiple values resulting from a combination of the respectively stored states of the first and second storage devices.
    Type: Application
    Filed: June 29, 2019
    Publication date: December 31, 2020
    Inventors: Ian A. YOUNG, Dmitri E. NIKONOV, Elijah V. KARPOV
  • Techniques for current-sensing circuit design for compute-in-memory
    Patent number: 10877752
    Abstract: A compute-in-memory (CIM) circuit that enables a multiply-accumulate (MAC) operation based on a current-sensing readout technique. An operational amplifier coupled with a bitline of a column of bitcells included in a memory array of the CIM circuit to cause the bitcells to act like ideal current sources for use in determining an analog voltage value outputted from the operational amplifier for given states stored in the bitcells and for given input activations for the bitcells. The analog voltage value sensed by processing circuitry of the CIM circuit and converted to a digital value to compute a multiply-accumulate (MAC) value.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil Knag, Ram Krishnamurthy, Sasikanth Manipatruni, Amrita Mathuriya, Abhishek Sharma, Ian A. Young
  • RECESSED GATE OXIDE ON THE SIDEWALL OF GATE TRENCH
    Publication number: 20200403081
    Abstract: Described is a transistor which includes: a source region; a drain region; and a gate region between the source and drain regions, wherein the gate region comprises: high-K dielectric material between spacers such that the high-K dielectric material is recessed; and metal electrode on the recessed high-K dielectric material. The gate recessed gate dielectric allows for using thick gate dielectric even with much advanced process technology nodes (e.g., 7 nm and below).
    Type: Application
    Filed: June 19, 2019
    Publication date: December 24, 2020
    Inventors: Seung Hoon Sung, Sou-Chi Chang, Ashish Verma Penumatcha, Nazila Haratipour, Matthew Metz, Michael Harper, Jack Kavalieros, Uygar Avci, Ian Young
  • FERROELECTRIC OR ANTI-FERROELECTRIC TRENCH CAPACITOR WITH SPACERS FOR SIDEWALL STRAIN ENGINEERING
    Publication number: 20200395460
    Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by providing tensile stress along a plane (e.g., x-axis) of a ferroelectric or anti-ferroelectric material of the ferroelectric/anti-ferroelectric based capacitor. Tensile stress is provided by a spacer comprising metal, semimetal, or oxide (e.g., metal or oxide of one or more of: Al, Ti, Hf, Si, Ir, or N). The tensile stress provides polar orthorhombic phase to the ferroelectric material and tetragonal phase to the anti-ferroelectric material. As such, memory window and reliability of the ferroelectric/anti-ferroelectric oxide thin film improves.
    Type: Application
    Filed: June 13, 2019
    Publication date: December 17, 2020
    Applicant: Intel Corporation
    Inventors: Nazila Haratipour, Sou-Chi Chang, Chia-Ching Lin, Jack Kavalieros, Uygar Avci, Ian Young
  • TRENCH CAPACITOR WITH EXTENDED DIELECTRIC LAYER
    Publication number: 20200395435
    Abstract: An improved trench capacitor structure is disclosed that allows for the formation of narrower capacitors. An example capacitor structure includes a first conductive layer on the sidewalls of an opening through a thickness of a dielectric layer, a capacitor dielectric layer on the first conductive layer, a second conductive layer on the capacitor dielectric layer, and a conductive fill material on the second conductive layer. The capacitor dielectric layer laterally extends above the opening and along a top surface of the dielectric layer, and the conductive fill material fills a remaining portion of the opening.
    Type: Application
    Filed: June 14, 2019
    Publication date: December 17, 2020
    Applicant: INTEL CORPORATION
    Inventors: NAZILA HARATIPOUR, CHIA-CHING LIN, SOU-CHI CHANG, IAN A. YOUNG, UYGAR E. AVCI, JACK T. KAVALIEROS
  • MAGNETIC MEMORY DEVICE WITH RUTHENIUM DIFFUSION BARRIER
    Publication number: 20200395406
    Abstract: A magnetic memory device comprising a plurality of memory cells is disclosed. The memory device includes an array of memory cells where each memory cell includes a first material layer having a ferromagnetic material, a second material layer having ruthenium, and a third material layer having bismuth and/or antimony. The second material layer is sandwiched between the first material layer and the third material in a stacked configuration.
    Type: Application
    Filed: June 17, 2019
    Publication date: December 17, 2020
    Applicant: INTEL CORPORATION
    Inventors: EMILY WALKER, CARL H. NAYLOR, KAAN OGUZ, KEVIN L. LIN, TANAY GOSAVI, CHRISTOPHER J. JEZEWSKI, CHIA-CHING LIN, BENJAMIN W. BUFORD, DMITRI E. NIKONOV, JOHN J. PLOMBON, IAN A. YOUNG, NORIYUKI SATO
  • Memory including a perovskite material
    Patent number: 10861861
    Abstract: An embodiment includes a system comprising: first, second, third, fourth, fifth, and sixth layers, (a) the second, third, fourth, and fifth layers being between the first and sixth layers, and (b) the fourth layer being between the third and fifth layers; a formation between the first and second layers, the formation including: (a) a material that is non-amorphous; and (b) first and second sidewalls; a capacitor between the second and sixth layers, the capacitor including: (a) the third, fourth, and fifth layers, and (b) an electrode that includes the third layer and an additional electrode that includes the fifth layer; and a switching device between the first and sixth layers; wherein: (a) the first layer includes a metal and the sixth layer includes the metal, and (b) the fourth layer includes a Perovskite material. Other embodiments are addressed herein.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: December 8, 2020
    Assignee: Intel Corporation
    Inventors: Chia-Ching Lin, Sasikanth Manipatruni, Tanay Gosavi, Dmitri Nikonov, Sou-Chi Chang, Uygar E. Avci, Ian A. Young
  • Binary, ternary and bit serial compute-in-memory circuits
    Patent number: 10860682
    Abstract: A binary CIM circuit enables all memory cells in a memory array to be effectively accessible simultaneously for computation using fixed pulse widths on the wordlines and equal capacitance on the bitlines. The fixed pulse widths and equal capacitance ensure that a minimum voltage drop in the bitline represents one least significant bit (LSB) so that the bitline voltage swing remains safely within the maximum allowable range. The binary CIM circuit maximizes the effective memory bandwidth of a memory array for a given maximum voltage range of bitline voltage.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: December 8, 2020
    Assignee: Intel Corporation
    Inventors: Phil Knag, Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Abhishek Sharma, Sasikanth Manipatruni, Amrita Mathuriya, Ram Krishnamurthy, Ian A. Young
  • NEURAL COMPUTING DIES WITH STACKED NEURAL CORE REGIONS
    Publication number: 20200373329
    Abstract: Disclosed herein are neural computing dies with stacked neural core regions as well as related methods and assemblies. In some embodiments, a neural computing die may include: a first neural core region; a second neural core region; and an inter-core interconnect region in a volume between the first neural core region and the second neural core region, wherein the inter-core interconnect region includes a conductive pathway between the first neural core region and the second neural core region, and the conductive pathway includes a conductive via.
    Type: Application
    Filed: August 10, 2020
    Publication date: November 26, 2020
    Applicant: Intel Corporation
    Inventors: Dmitri E. Nikonov, Clifford Lu Ong, Ian A. Young
  • STAGED OSCILLATORS FOR NEURAL COMPUTING
    Publication number: 20200372333
    Abstract: Disclosed herein are staged oscillators for neural computing, as well as related methods and assemblies. In some embodiments, neural computing circuitry may include a first oscillator set, a second oscillator set, and an averaging structure coupled between the first oscillator set and the second oscillator set.
    Type: Application
    Filed: August 10, 2020
    Publication date: November 26, 2020
    Applicant: Intel Corporation
    Inventors: Dmitri E. Nikonov, Hai Li, Ian A. Young
  • Digital bit-serial multi-multiply-and-accumulate compute in memory
    Patent number: 10831446
    Abstract: A memory device that includes a plurality subarrays of memory cells to store static weights and a plurality of digital full-adder circuits between subarrays of memory cells is provided. The digital full-adder circuit in the memory device eliminates the need to move data from a memory device to a processor to perform machine learning calculations. Rows of full-adder circuits are distributed between sub-arrays of memory cells to increase the effective memory bandwidth and reduce the time to perform matrix-vector multiplications in the memory device by performing bit-serial dot-product primitives in the form of accumulating m 1-bit×n-bit multiplications.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: November 10, 2020
    Assignee: Intel Corporation
    Inventors: Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil Knag, Ram Krishnamurthy, Sasikanth Manipatruni, Amrita Mathuriya, Abhishek Sharma, Ian A. Young
  • Polarization gate stack SRAM
    Patent number: 10832761
    Abstract: One embodiment provides an apparatus. The apparatus includes a first inverter comprising a first pull up transistor and a first pull down transistor; a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor; a first access transistor coupled to the first inverter; and a second access transistor coupled to the second inverter. A gate electrode of one transistor of each inverter comprises a polarization layer.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: November 10, 2020
    Assignee: Intel Corporation
    Inventors: Daniel H. Morris, Uygar E. Avci, Ian A. Young