Patents by Inventor Ibrahim Ban

Ibrahim Ban has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9786667
    Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: October 10, 2017
    Assignee: Intel Corporation
    Inventors: Peter L. D. Chang, Uygar E. Avci, David Kencke, Ibrahim Ban
  • Publication number: 20170207222
    Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.
    Type: Application
    Filed: March 30, 2017
    Publication date: July 20, 2017
    Inventors: Peter L. D. Chang, Uygar E. Avci, David Kencke, Ibrahim Ban
  • Patent number: 9664858
    Abstract: Systems and methods may couple on-chip optical circuits to external fibers. An SOI waveguide structure may include mirror structures and tapered waveguides to optically couple optical circuits to fibers in a vertically oriented external connector. The mirror structure(s) may be angularly disposed at the ends of the silicon waveguide structure. An oxide layer may cover a buried oxide layer and the silicon waveguide structure. The tapered waveguide(s) may have a narrow end and a wide end. The narrow end of the tapered waveguide(s) may be disposed above the mirror structures. The tapered waveguide(s) may extend through the oxide layer from the narrow end in a direction perpendicular to the silicon waveguide structure. An external connector may fit over the tapered waveguide(s) and uses a fiber array traveling through a connector body to optically couple to the external fiber.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: May 30, 2017
    Assignee: Intel Corporation
    Inventors: Edris M. Mohammed, Peter L. Chang, Ibrahim Ban
  • Patent number: 9646970
    Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: May 9, 2017
    Assignee: Intel Corporation
    Inventors: Peter L. D. Chang, Uygar E. Avci, David Kencke, Ibrahim Ban
  • Patent number: 9618824
    Abstract: Systems and methods may provide for an integrated miniature sensor that operates in the Terahertz region of the electromagnetic spectrum. The integrated miniature sensor may detect a remote target and operate in a non-contact, non-invasive manner. Numerous signal analysis techniques may be employed such as Doppler radar technology, absorption spectroscopy, and others when the integrated miniature sensor is used in biomedical, physiological and other settings where prolonged recording of bio-signals is needed.
    Type: Grant
    Filed: September 27, 2014
    Date of Patent: April 11, 2017
    Assignee: Intel Corporation
    Inventors: Edris M. Mohammed, Ibrahim Ban
  • Publication number: 20170062434
    Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.
    Type: Application
    Filed: November 11, 2016
    Publication date: March 2, 2017
    Inventors: Peter L. D. Chang, Uygar E. Avci, David Kencke, Ibrahim Ban
  • Patent number: 9520399
    Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: December 13, 2016
    Assignee: Intel Corporation
    Inventors: Peter L. D. Chang, Uygar E. Avci, David Kencke, Ibrahim Ban
  • Publication number: 20160322360
    Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which alloys the different oxide and gate materials to he fabricated is described.
    Type: Application
    Filed: July 13, 2016
    Publication date: November 3, 2016
    Inventors: Peter L. D. Chang, Uygar E. Avci, David Kencke, Ibrahim Ban
  • Patent number: 9418997
    Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to he fabricated is described.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: August 16, 2016
    Assignee: Intel Corporation
    Inventors: Peter L. D. Chang, Uygar E. Avci, David Kencke, Ibrahim Ban
  • Publication number: 20160155742
    Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which alloys the different oxide and gate materials to he fabricated is described.
    Type: Application
    Filed: February 5, 2016
    Publication date: June 2, 2016
    Inventors: Peter L. D. Chang, Uygar E. Avci, David Kencke, Ibrahim Ban
  • Publication number: 20160091776
    Abstract: Systems and methods may provide for an integrated miniature sensor that operates in the Terahertz region of the electromagnetic spectrum. The integrated miniature sensor may detect a remote target and operate in a non-contact, non-invasive manner. Numerous signal analysis techniques may be employed such as Doppler radar technology, absorption spectroscopy, and others when the integrated miniature sensor is used in biomedical, physiological and other settings where prolonged recording of bio-signals is needed.
    Type: Application
    Filed: September 27, 2014
    Publication date: March 31, 2016
    Inventors: Edris M. Mohammed, Ibrahim Ban
  • Patent number: 9275999
    Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: March 1, 2016
    Assignee: Intel Corporation
    Inventors: Peter L. D. Chang, Uygar E. Avci, David Kencke, Ibrahim Ban
  • Patent number: 9182544
    Abstract: PLC architectures and fabrication techniques for providing electrical and photonic integration of a photonic components with a semiconductor substrate. In the exemplary embodiment, the PLC is to accommodate optical input and/or output (I/O) as well as electrically couple to a microelectronic chip. One or more photonic chip or optical fiber terminal may be coupled to an optical I/O of the PLC. In embodiments the PLC includes a light modulator, photodetector and coupling regions supporting the optical I/O. Spin-on electro-optic polymer (EOP) may be utilized for the modulator while a photodefinable material is employed for a mode expander in the coupling region.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: November 10, 2015
    Assignee: Intel Corporation
    Inventors: Mauro J. Kobrinsky, Miriam R. Reshotko, Ibrahim Ban, Bruce A. Block, Peter L. Chang
  • Publication number: 20150179650
    Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.
    Type: Application
    Filed: March 6, 2015
    Publication date: June 25, 2015
    Inventors: Peter L. D. Chang, Uygar E. Avci, David Kencke, Ibrahim Ban
  • Patent number: 8980707
    Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: March 17, 2015
    Assignee: Intel Corporation
    Inventors: Peter L. D. Chang, Uygar E. Avci, David Kencke, Ibrahim Ban
  • Publication number: 20140177995
    Abstract: Systems and methods may couple on-chip optical circuits to external fibers. An SOI waveguide structure may include mirror structures and tapered waveguides to optically couple optical circuits to fibers in a vertically oriented external connector. The mirror structure(s) may be angularly disposed at the ends of the silicon waveguide structure. An oxide layer may cover a buried oxide layer and the silicon waveguide structure. The tapered waveguide(s) may have a narrow end and a wide end. The narrow end of the tapered waveguide(s) may be disposed above the mirror structures. The tapered waveguide(s) may extend through the oxide layer from the narrow end in a direction perpendicular to the silicon waveguide structure. An external connector may fit over the tapered waveguide(s) and uses a fiber array traveling through a connector body to optically couple to the external fiber.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Inventors: Edris M. Mohammed, Peter L. Chang, Ibrahim Ban
  • Patent number: 8731346
    Abstract: Embodiments of the present disclosure provide optical connection techniques and configurations. In one embodiment, an apparatus includes a substrate, a laser device formed on the substrate, the laser device including an active layer configured to emit light, and a mode-expander waveguide disposed on the substrate and butt-coupled with the active layer to receive and route the light to a waveguide formed on another substrate. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: May 20, 2014
    Assignee: Intel Corporation
    Inventors: Jia-Hung Tseng, Peter L. Chang, Miriam R. Reshotko, Ibrahim Ban, Mauro J. Kobrinsky, Brian Corbett, Roberto Pagano
  • Publication number: 20140086527
    Abstract: An optical coupler includes a double-sided planar substrate having a lens manufactured on one side and a mode expander on the other side. The mode expander is coupled to a mirror that redirects light between the mode expander and the lens. The mirror is lithographically aligned with the lens. The substrate is optically transparent to a target wavelength to be used for optical signaling. The lens can be a lens array, in which case there can be a mirror for each lens in the array. The mode expander can couple an optical signal to a planar lightwave circuit (PLC) or other optical circuit. The lens on the optical coupler can interface with a single-mode optical fiber.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Inventors: Ibrahim Ban, Peter L. Chang
  • Publication number: 20140015021
    Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.
    Type: Application
    Filed: September 16, 2013
    Publication date: January 16, 2014
    Inventors: Peter L. D. Chang, Uygar E. Avci, David Kencke, Ibrahim Ban
  • Publication number: 20140003765
    Abstract: Embodiments of the present disclosure provide optical connection techniques and configurations. In one embodiment, an apparatus includes a substrate, a laser device formed on the substrate, the laser device including an active layer configured to emit light, and a mode-expander waveguide disposed on the substrate and butt-coupled with the active layer to receive and route the light to a waveguide formed on another substrate. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 2, 2014
    Inventors: Jia-Hung Tseng, Peter L. Chang, Miriam R. Reshotko, Ibrahim Ban, Mauro J. Kobrinsky, Brian Corbett, Roberto Pagano