Abstract: A transistor formed in a semiconductor substrate is provided with a cooling trench. The cooling trench is elongated and extends laterally from a first end of an elongated gate electrode disposed above a channel region of the transistor to a second end of the gate electrode in a first direction that is parallel to a top surface of the semiconductor substrate. The cooling trench is coupled to the first current terminal and extends laterally from a first end to a second end of the first elongated cooling trench along the first direction and extends vertically from the first current terminal and through the top surface into the semiconductor substrate. The cooling trench is filled throughout with a thermally-conductive material configured to dissipate heat from the channel region into the semiconductor substrate.

Abstract: A transistor die includes input and output terminals and a source through-substrate via (TSV) between the input and output terminals. First and second primary drain contacts extend from the output terminal toward the input terminal past first and second sides, respectively, of the source TSV. An ancillary region is located adjacent to the source TSV, and boundaries of the ancillary region are defined by the source TSV, the first and second drain contacts, and one of the input terminal or the output terminal. The transistor further includes a primary transistor element, including a primary drain contact, a primary source contact, and a primary gate structure, located outside of the first ancillary region, and an ancillary transistor element, including an ancillary drain contact, an ancillary source contact, and an ancillary gate structure, located within the ancillary region.

Abstract: An amplifier module includes a module substrate with a mounting surface, a signal conducting layer, a ground layer, and a ground terminal pad at the mounting surface. A thermal dissipation structure extends through the module substrate. A ground contact of a power transistor die is coupled to a surface of the thermal dissipation structure. Encapsulant material covers the mounting surface of the module substrate and the power transistor die, and a surface of the encapsulant material defines a contact surface of the amplifier module. A ground terminal is embedded within the encapsulant material. The ground terminal has a proximal end coupled to the ground terminal pad, and a distal end exposed at the contact surface. The ground terminal is electrically coupled to the ground contact of the power transistor die through the ground terminal pad, the ground layer of the module substrate, and the thermal dissipation structure.

Abstract: Flow control elements (FCEs) and fluid apparatus including the same are described. In embodiments the flow control elements (FCE) include a body that includes a front side, a back side, a left side, and a right side. The body further includes a base region, an upper region, and an intermediate region between the base region and the upper region. The FCE is configured to move in response to a fluid flow (or, more specifically, a pressure differential across the FCE) to regulate a flow of fluid past the FCE. In embodiments the FCE is included in a fluid apparatus for a vehicle, such as but not limited to a suction filter for a vehicle transmission.

Abstract: A device having a reference transistor fabricated within the same semiconductor substrate as a primary transistor (e.g., configured for use in a radiofrequency amplifier or other active circuit) has a shared metallization area coupled to a current terminal of both transistors configured to shield a control terminal of the reference transistor from coupling of alternating current interference from alternating currents within the primary transistor.

Abstract: A transistor includes a source contact connected to a Through-Silicon Via (TSV). A drain contact is connected to a first pad. A gate structure is interposed between the source contact and the drain contact. A second pad is connected to the gate structure, the second pad comprising a first side diametrically opposed to a second side, and a third side interposed therebetween, the source contact proximal to the third side, a first portion of the first side and a second portion of the second side.

Abstract: A device includes a semiconductor substrate, a source metallization over an active area of the semiconductor substrate, a through-substrate via electrically connected to the source metallization, and an input bond pad formed in the semiconductor substrate and spaced apart from the active area. The input bond pad is electrically connected to a set of gate structures. The device includes a first inductive coil over the semiconductor substrate between a first portion of the source metallization and a second portion of the source metallization and a first capacitor over the semiconductor substrate between the first portion of the source metallization and the second portion of the source metallization. The first inductive coil and the first capacitor are connected in series between the input bond pad and the through-substrate via.

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate, a first dielectric layer, a first current-carrying electrode, and a second current-carrying electrode formed over the semiconductor substrate. A control electrode is formed over the semiconductor substrate and disposed between the first current-carrying electrode and the second current-carrying electrode. A conductive element formed over the first dielectric layer, adjacent the control electrode, and between the control electrode and the second current-carrying electrode, includes a first region formed a first distance from the upper surface of the semiconductor substrate and a second region formed a second distance from the upper surface of the semiconductor substrate. An insulating region is formed between the control electrode and the conductive element.

Abstract: A semiconductor device includes a semiconductor substrate, a first dielectric layer disposed over the upper surface of the semiconductor substrate, a second dielectric layer disposed over the first dielectric layer, a third dielectric layer disposed over the second dielectric layer, a lower opening formed in the first dielectric layer, an upper opening formed in the second dielectric layer and the third dielectric layer, wherein at least a portion of the upper opening overlaps a portion of the lower opening, and a control electrode formed within at least a portion of the lower opening and within a portion of the upper opening, wherein a portion of the control electrode is formed over the third dielectric layer.

Abstract: Placement of a field plate in a field-effect transistor is optimized by using multiple dielectric layers such that a first end of field plate is separated from a channel region of the transistor by a first set of one or more distinct dielectric material layers. A second end of the field plate overlies the channel region and a control electrode from which it is separated by the first set of dielectric layers and one or more additional dielectric layers. Relative positioning of the control electrode and the field plate are determined by a single processing step such that the field plate is self-aligned to the control electrode in order to reduce variations in transistor performance associated with manufacturing process variations.

Abstract: System and method of analyzing a video, comprising dividing the video into a set of successive basic units; generating semantic tags for the basic units using a set of hierarchical classifier nodes that comprise a parent classifier node and a plurality of child classifier nodes, wherein the basic units are each routed through selected child classifier nodes based on classification of the basic units by the parent classifier node; and generating a semantic topic for the video based on the semantic tags generated for the basic units.

Abstract: Flow control elements (FCEs) and fluid apparatus including the same are described. In embodiments the flow control elements (FCE) include a body that includes a front side, a back side, a left side, and a right side. The body further includes a base region, an upper region, and an intermediate region between the base region and the upper region. The FCE is configured to move in response to a fluid flow (or, more specifically, a pressure differential across the FCE) to regulate a flow of fluid past the FCE. In embodiments the FCE is included in a fluid apparatus for a vehicle, such as but not limited to a suction filter for a vehicle transmission.

Abstract: A transistor includes a source contact connected to a Through-Silicon Via (TSV). A drain contact is connected to a first pad. A gate structure is interposed between the source contact and the drain contact. A second pad is connected to the gate structure, the second pad comprising a first side diametrically opposed to a second side, and a third side interposed therebetween, the source contact proximal to the third side, a first portion of the first side and a second portion of the second side.

Abstract: Methods, systems, and media for image searching are described. Images comprising one query image and a plurality of candidate images are received. For each candidate image, a first model similarity measure from an output of a first model configured for scene classification to perceive scenes in the images is determined. Further, for each candidate image of the plurality of candidate images, a second model similarity measure from the output of a second model configured for attribute classification to perceive attributes in the images is determined. For each candidate image of the plurality of candidate images, a similarity agglomerate index of a weighted aggregate of the first model similarity measure and the second model similarity measure is computed. The plurality of candidate images based on the respective similarity agglomerate index of each candidate image are ranked and a first ranked candidate images corresponding to the searched images are generated.

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate, a first current-carrying electrode, and a second current-carrying electrode formed over the semiconductor, a control electrode formed over the semiconductor substrate between the first current carrying electrode and the second current carrying electrode, and a first dielectric layer disposed over the control electrode, and a second dielectric layer disposed over the first dielectric layer. A first opening is formed in the second dielectric layer, adjacent the control electrode and the second current-carrying electrode, having a first edge laterally adjacent to and nearer the second current-carrying electrode, and a second edge laterally adjacent to and nearer to the control electrode, and a conductive element formed over the first dielectric layer and within the first opening, wherein the portion of the conductive element formed within the first opening forms a first metal-insulator-semiconductor region within the first opening.

Abstract: A semiconductor device includes a die body having a frontside and a transistor having an active area formed in the die body, the active area being bounded by an outer periphery. An interconnect structure is formed over the frontside of the die body and contains patterned electrically conductive material defining first, second, and third contacts electrically coupled to first, second, and third subregions, respectively, within the active area of the transistor. A frontside input/output (I/O) interface is formed in an outer portion of the interconnect structure. The frontside I/O interface contains first, second, and third contact pads, the first contact pad being electrically connected to the first contact, the second contact pad being electrically connected to the second contact, and the third contact pad being electrically connected the third contact, wherein the third contact pad is positioned at a location overlying the active area of the transistor.

Abstract: A power transistor die includes a semiconductor die with input and output die sides, and a transistor integrally formed in the semiconductor die between the input die side and the output die side, where the transistor has an input and an output (e.g., a gate and a drain, respectively). The power transistor die also includes an input bondpad and a first output bondpad integrally formed in the semiconductor die between the input die side and the transistor. The input bondpad is electrically connected to the input of the transistor. A conductive structure directly electrically connects the output of the transistor to the first output bondpad. A second output bondpad, which also may be directly electrically connected to the transistor output, may be integrally formed in the semiconductor die between the transistor and the output die side.

Abstract: A semiconductor device includes a semiconductor substrate, a first current-carrying electrode, a second current-carrying electrode, a first control electrode disposed between the first current-carrying electrode and the second current-carrying electrode, a third current-carrying electrode electrically coupled to the first current-carrying electrode, and a fourth current-carrying electrode adjacent the third current-carrying electrode. The third current-carrying electrode and the fourth current-carrying electrode are configured to support current flow from the third current-carrying electrode to the fourth current-carrying electrode parallel to a second direction. The fourth current-carrying element is electrically coupled to the second current-carrying electrode and a second control electrode. The second control electrode is electrically coupled to the first control electrode.

Abstract: A transistor includes a semiconductor substrate having first and second terminals. An interconnect structure, on an upper surface of the substrate, is formed of layers of dielectric material and electrically conductive material. The conductive material includes a first pillar connected with the first terminal, a second pillar connected with the second terminal, and a shield system between the first and second pillars. The shield system includes forked structures formed in at least two conductive layers of the interconnect structure and at least partially surrounding segments of the second pillar. The shield system may additionally include shield traces formed in a first conductive layer positioned between gate fingers and the first pillars and/or the shield system may include shield runners that are located in an electrically conductive layer that is below a topmost electrically conductive layer with the first pillar being connected to a runner in the topmost conductive layer.

Abstract: Methods and systems for updating the weights of a set of convolution kernels of a convolutional layer of a neural network are described. A set of convolution kernels having attention-infused weights is generated by using an attention mechanism based on characteristics of the weights. For example, a set of location-based attention multipliers is applied to weights in the set of convolution kernels, a magnitude-based attention function is applied to the weights in the set of convolution kernels, or both. An output activation map is generated using the set of convolution kernels with attention-infused weights. A loss for the neural network is computed, and the gradient is back propagated to update the attention-infused weights of the convolution kernels.