Patents by Inventor Ic-Su Oh

Ic-Su Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090045862
    Abstract: A clock generating circuit of a semiconductor memory apparatus includes a phase splitter that delays a clock to generate a delayed clock and inverts the clock to generate an inverted clock, and a clock buffer that buffers the delayed clock and the inverted clock and outputs a rising clock and a falling clock.
    Type: Application
    Filed: July 2, 2008
    Publication date: February 19, 2009
    Applicant: HYNIX SEMICONDUCTOR, INC.
    Inventors: Yong Ju Kim, Kun Woo Park, Dae Han Kwon, Hee Woong Song, Ic Su Oh, Hyung Soo Kim, Tae Jin Hwang, Hae Rang Choi, Ji Wang Lee
  • Publication number: 20090041172
    Abstract: A phase detection circuit includes a phase frequency detector for comparing a first input signal and a second input signal and outputting a first phase comparison signal and a second phase comparison signal, and a sensing circuit for sensing a pulse width difference between the first phase comparison signal and the second phase comparison signal and outputting phase detection signals which have different logic values.
    Type: Application
    Filed: January 23, 2008
    Publication date: February 12, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Yong Ju Kim, Kun Woo Park, Jong Woon Kim, Hee Woong Song, Ic Su Oh, Hyung Soo Kim, Tae Jin Hwang
  • Publication number: 20090041154
    Abstract: An apparatus for transmitting a signal in a semiconductor integrated circuit includes a multilevel transmission control block that outputs a plurality of bits of an input signal in serial or parallel according to whether a multilevel transmission operation is performed or not, and a signal processing block that selectively performs the multilevel transmission operation according to a form of the input signal, which are output in serial or parallel from the multilevel transmission control block.
    Type: Application
    Filed: December 28, 2007
    Publication date: February 12, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Hyung Soo Kim, Kun Woo Park, Yong Ju Kim, Jong Woon Kim, Hee Woong Song, Ic Su Oh, Tae Jin Hwang
  • Publication number: 20090002040
    Abstract: A DLL circuit for a semiconductor memory apparatus includes a delay line having a coarse delay chain, which has a plurality of coarse delayers connected in series and is inputted with a reference clock signal, and a plurality of fine delayers which receive output clock signals of the respective coarse delayers, and a delay control section for comparing phases of an output clock signal of a final coarse delayer among the coarse delayers with the reference clock signal and generating coarse control signals for controlling the coarse delayers and for comparing phases of an output clock signal of a fine delayer inputted with the output clock signals of the final coarse delayer, as a fine feedback clock signal, with the reference clock signal and generating fine control signals for controlling the fine delayers.
    Type: Application
    Filed: December 27, 2007
    Publication date: January 1, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Ic Su Oh, Kun Woo Park, Yong Ju Kim, Jong Woon Kim, Hee Wong Song, Hyung Soo Kim, Tae Jin Hwang
  • Publication number: 20080252341
    Abstract: A clock signal distribution circuit comprises a voltage control and distribution circuit configured to change a delay of a received clock signal in response to a control voltage and to generate a distributed clock signal, and control voltage generation circuit configured to generate the control voltage using a phase difference between received data and the distributed clock signal.
    Type: Application
    Filed: December 21, 2007
    Publication date: October 16, 2008
    Applicant: HYNIX SEMINCONDUCTOR, INC.
    Inventors: Yong-Ju Kim, Kun-Woo Park, Jong-Woon Kim, Hee-Woong Song, Ic-Su Oh, Hyung-Soo Kim, Tae-Jin Hwang
  • Publication number: 20080252353
    Abstract: A voltage measuring apparatus for a semiconductor integrated circuit includes a first delay unit configured to delay a reference clock in a first region, a second delay unit configured to delay the reference clock in a second region and an analysis unit configured to analyze a difference in voltage level between the regions based on the phases of associated with the delayed clock signals generated by the first and second delay units.
    Type: Application
    Filed: December 20, 2007
    Publication date: October 16, 2008
    Applicant: HYNIX SEMINCONDUCTOR, INC.
    Inventors: Hyung Soo Kim, Yong Ju Kim, Jong Woon Kim, Hee Woong Song, Ic Su Oh, Tae Jin Hwang
  • Publication number: 20080191776
    Abstract: A signal receiver circuit includes a first level detector for offset-controlling a first output node in response to a pair of first reference signals. A second level detector offset-controls a second output node in response to a pair of second reference signals.
    Type: Application
    Filed: December 18, 2007
    Publication date: August 14, 2008
    Applicant: HYNIX SEMINCONDUCTOR, INC.
    Inventors: Hee Woong Song, Kun Woo Park, Yong Ju Kim, Jong Woon Kim, Ic Su Oh, Hyung Soo Kim, Tae Jin Hwang
  • Patent number: 7394285
    Abstract: A bus driving circuit includes a majority voter unit for comparing the number of logic high level bits with the number of logic low level bits among a predetermined number of bits of data; a latch unit for latching a first output signal in response to the compared result; and a flip-flop unit for latching the predetermined number of bits of data in synchronization with the clock; and a selection unit for selecting one of the latched data of the flip-flop unit and an inverted output of the latched data of the flip-flop unit according to the first output signal.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: July 1, 2008
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Ic-Su Oh, Yong-Ju Kim
  • Publication number: 20080088360
    Abstract: A power supply apparatus of a semiconductor integrated circuit includes a power control device that detects a level of power supplied from the outside and outputs a control signal as information on the detected level, and a power supply device that controls an internal resistance component in response to an input of the control signal, controls the level of the power supplied from the outside, and supplies the power having the controlled level to circuit blocks.
    Type: Application
    Filed: July 3, 2007
    Publication date: April 17, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Hyung Soo Kim, Kun Woo Park, Yong Ju Kim, Ic Su Oh, Hee Woong Song, Jong Woon Kim, Tae Jin Hwang
  • Publication number: 20080068058
    Abstract: A PLL circuit includes a phase detector that compares the phase of an input clock and the phase of a feedback clock and generates a pull-up control signal and a pull-down control signal. A loop filter pumps a voltage in response to the pull-up and pull-down control signals, filters the pumped voltage, and outputs a control voltage. A voltage controlled oscillator receives the control signal and oscillates an output clock. A clock divider divides the frequency of the output clock at a predetermined rate to generate the feedback clock. In the PLL circuit, the loop filter includes a compensator that compensates for a variation.
    Type: Application
    Filed: July 2, 2007
    Publication date: March 20, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Yong Ju Kim, Kun Woo Park, Jong Woon Kim, Hee Woong Song, Ic Su Oh, Hyung Soo Kim, Tae Jin Hwang
  • Publication number: 20080068057
    Abstract: A PLL circuit includes a phase detector that compares the phase of an input clock with the phase of a feedback clock so as to generate pull-up and pull-down control signals. A low pass filter pumps a voltage in response to the pull-up and pull-down control signals, and removes a noise component from the pumped voltage so as to output a control voltage. A buffer that controls voltage so as to generate a bias voltage having a smaller swing width than the control voltage. A voltage controlled oscillator receives the bias voltage and oscillates an output clock. A clock divider divides the frequency of the output clock at a predetermined ratio so as to generate the feedback clock.
    Type: Application
    Filed: June 28, 2007
    Publication date: March 20, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Yong Ju Kim, Kun Woo Park, Jong Woon Kim, Hee Woong Song, Ic Su Oh, Hyung Soo Kim, Tae Jin Hwang
  • Publication number: 20080061840
    Abstract: A receiver circuit includes an offset control signal generating unit that outputs a plurality of offset control signals using an offset voltage. A sense amplifier receives a first current and a second current generated on the basis of an up input signal and a down input signal, respectively, converts the first current and the second current into an up compensating signal and a down compensating signal having electric potentials compensating the offset voltage, and amplifies the up compensating signal and the down compensating signal to output an up output signal and a down output signal.
    Type: Application
    Filed: July 6, 2007
    Publication date: March 13, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Tae Jin Hwang, Kun Woo Park, Yong Ju Kim, Jong Woon Kim, Hee Woong Song, Ic Su Oh, Hyung Soo Kim
  • Publication number: 20070194818
    Abstract: A phase locked loop circuit and a control method thereof. A phase locked loop circuit includes a phase detecting and correcting block configured to detect a phase difference between a reference clock and a feedback clock, and to correct the phase of the feedback clock such that the phase of the reference clock and the phase of the feedback clock are consistent with each other, and an initial locking level setting block configured to set a locking level in a normal operation mode in the phase detecting and correcting block. The initial locking level setting block includes a digital-to-analog converting unit configured to generate an analog voltage according to a digital code corresponding to the set frequency, and charges the capacitive element with the analog voltage, and a switching unit configured to connect the digital-to-analog converting unit and the capacitive element in response to an input of an operation start signal.
    Type: Application
    Filed: December 19, 2006
    Publication date: August 23, 2007
    Applicant: Hynix Semiconductor Inc.
    Inventors: Yong-Ju Kim, Kun-Woo Park, Hyung-Soo Kim, Ic-Su Oh, Hee-Woong Song, Jong-Woon Kim, Tae-Jin Hwang
  • Publication number: 20070069589
    Abstract: A bus driving circuit includes a majority voter unit for comparing the number of logic high level bits with the number of logic low level bits among a predetermined number of bits of data; a latch unit for latching a first output signal in response to the compared result; and a flip-flop unit for latching the predetermined number of bits of data in synchronization with the clock; and a selection unit for selecting one of the latched data of the flip-flop unit and an inverted output of the latched data of the flip-flop unit according to the first output signal.
    Type: Application
    Filed: June 30, 2006
    Publication date: March 29, 2007
    Inventors: Ic-Su Oh, Yong-Ju Kim