Abstract: A data output circuit for a semiconductor memory apparatus includes a driver control signal generating unit that has a plurality of control signal generating units, each of which generates a driver unit control signal in response to a test signal during a test, and generates the driver unit control signal according to whether or not a fuse is cut after the test is completed, a first driver that has a plurality of driver units, each of which is activated in response to the driver unit control signal to drive a first data signal as an input signal and to output the driven first data signal to an output node, a signal combining unit that generates a first driver control signal in response to the driver unit control signal and an enable signal, and a second driver that has a plurality of driver units, each of which is activated in response to the first driver control signal to drive a second data signal as an input signal and to output the driven second data signal to the output node, and the number of driver uni

Abstract: Disclosed is an output driver capable of solving problems that occur when outputting the same data successively by using a data pattern detecting circuit. The data pattern detecting circuit includes a first data storage unit configured to receive data of a first line and store the received data until a next data is inputted through the first line, a second data storage unit configured to receive data of a second line and store the received data until a next data is inputted through the second line, and a detection signal output unit configured to activate a pattern detection signal when data stored in the first data storage unit and data stored in the second data storage unit have the same logic level.

Abstract: A data output circuit includes a pre-driving block configured to receive input data, generate a plurality of pull-up signals and pull-down signals, and change enable times of the pull-up signals and the pull-down signals in response to a plurality of control signals, and a main driving block configured to generate output data in response to the pull-up signals and the pull-down signals.

Abstract: A data center tracking circuit includes a clock tree, a sensing block, and a delay compensation block. The clock tree includes a plurality of clock buffers connected in series, buffers a clock, and outputs an output signal. The sensing block senses the phase change of the output signal on the basis of the clock, and outputs a sensing signal. The delay compensation block adjusts current to be supplied to the clock tree in response to the sensing signal, and adjusts the phase of the output signal.

Abstract: A duty cycle correction circuit includes a signal generating unit including a first signal generating unit coupled to a power supply voltage terminal and configured to output a complementary output signal of an output signal in response to a clock signal, and a second signal generating unit coupled to the power supply voltage terminal and configured to output the output signal in response to a complementary clock signal of the clock signal; a variable resistor unit coupled between the first and second signal generating units configured to vary an amount of current flowing into the signal generating unit according to a duty correction control signal, the duty correction control signal having a voltage level determined based on a voltage level of the output signal; and a current source coupled between the variable resistor unit and a ground voltage terminal configured to supply current to the signal generating unit.

Abstract: A semiconductor integrated circuit includes a voltage supplying unit that supplies a first regulated voltage and a second regulated voltage by using a first reference voltage and a second reference voltage, respectively, and a clock buffer unit that supplies an output clock clocking within a range of the first regulated voltage and the second regulated voltage.

Abstract: A phase mixer includes a phase mixing unit configured to mix a phase of a first input signal and a phase of a second input signal in response to a phase control signal and output a phase mixed signal whose phase is varied by one or more units of a unit phase value, and a phase value adjusting unit configured to control an operation of the phrase mixing unit so that the unit phase value is adjusted in response to a code signal coding at least one of a process, voltage, or temperature (PVT) variation.

Abstract: A variable delay circuit includes at least a fixed delay unit, a first selection unit, and variable delay unit. The fixed delay unit receives an input signal and a first delay selection signal indicative of a first delay, and outputs a first delayed signal that is substantially the input signal delayed by the first delay. The first selection unit receives the input signal, the first delayed signal, and a second delay selection signal, and outputs either the input signal or the first delayed signal based on the second delay selection signal to the variable delay unit. The variable delay unit also receives a third delay selection signal indicative of a third delay, and outputs a output signal that is substantially the output signal of the selection unit delayed by a third delay. The first delay is 0 or X multiples of M delay units. The third delay is a delay selected from 0 to N delay units.

Abstract: An internal supply voltage generating circuit includes a clock comparator configured to compare a first clock signal having clock information corresponding to a level of a reference voltage with a second clock signal having clock information corresponding to a level of an internal supply voltage, a control signal generator configured to generate a driving control voltage having a voltage level corresponding to an output signal of the clock comparator; and a driver configured to drive a terminal of the internal supply voltage in response to the driving control voltage.

Abstract: A PLL circuit includes a phase detector that compares the phase of an input clock and the phase of a feedback clock and generates a pull-up control signal and a pull-down control signal. A loop filter pumps a voltage in response to the pull-up and pull-down control signals, filters the pumped voltage, and outputs a control voltage. A voltage controlled oscillator receives the control signal and oscillates an output clock. A clock divider divides the frequency of the output clock at a predetermined rate to generate the feedback clock. In the PLL circuit, the loop filter includes a compensator that compensates for a variation.

Abstract: The domain crossing circuit of a semiconductor memory apparatus for improving a timing margin includes a sampler that provides a sampling internal signal generated by delaying an internal input signal by a predetermined time in response to a clock and an edge information signal that defines an output timing of the sampling internal signal and an output stage that allows the sampling internal signal to be synchronized with the clock in response to the edge information signal to be output as a final output signal.

Abstract: A receiver circuit is described herein, comprising a first data determining unit configured to detect and amplify a voltage level difference between first and second external data and generate first and second sense signals and to generate first internal data in response to the first and second sense signals, a first offset control unit configured to generate first and second offset signals in response to the first and second sense signals, the first and second offset signals swinging between a maximum voltage level and a minimum voltage level determined based on a first code, a second data determining unit configured to detect and amplify the voltage level difference between the first and second external data to generate third and fourth sense signals and to generate second internal data in response to the third and fourth sense signals; and a second offset control unit for generating third and fourth offset signals in response to the third and fourth sense signals, the third and fourth offset signals swingi

Abstract: A signal receiver circuit includes a first level detector for offset-controlling a first output node in response to a pair of first reference signals. A second level detector offset-controls a second output node in response to a pair of second reference signals.

Abstract: A duty cycle correction apparatus includes a fixed delay unit configured to set a fixed delay time to a DLL clock signal and generate a delay rising clock signal; a variable delay unit configured to delay the DLL clock signal in response to a control signal and generate a delay falling clock signal; a duty cycle correction unit configured to generate a correction rising clock signal and a correction falling clock signal that are toggled in conformity with edge timing of the delay rising clock signal and the delay falling clock signal; and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal and generate the control signal.

Abstract: A delay locked loop (DLL) circuit includes a phase detection unit configured to generate a phase detection signal by comparing a phase of a reference clock signal with a phase of a feedback clock signal. An update control apparatus is configured to generate a valid interval signal and an update control signal by determining a difference between the number of first logical values and the number of second logical values of the phase detection signal in response to the reference clock signal. A shift register configured to update a delay value granted to a delay line in response to the update control signal when the valid interval signal is enabled.

Abstract: A data receiver of a semiconductor integrated circuit is configured to detect received data using an equalization function, wherein the data receiver is configured to stop the equalization function during a period in which the data is not received.

Abstract: A DLL circuit includes a multiphase clock signal generating unit configured to produce a plurality of multiphase clock signals by delaying a reference clock signal for a unit delay time and to produce an enable signal that is enabled when one of the plurality of the multiphase clock signals synchronizes with the reference clock signal at a frequency, and a multiphase clock signal selecting unit configured to delay one of the plurality of the multiphase clock signals for a predetermined time in response to a first control signal, to compare a phase of a delayed multiphase clock signal with a phase of the reference clock signal, and to output one of the plurality of the multiphase clock signals as a delayed clock signal, wherein a phase of the delayed clock signal synchronizes with the phase of the reference clock signal when the enable signal is enabled.

Abstract: A semiconductor integrated circuit comprises a PLL (Phase Locked Loop (PLL) circuit configured to generate a control voltage in response to a frequency of a reference clock signal, and to generate a PLL clock signal having a frequency that corresponds to a level of the control voltage, and a voltage controlled oscillator configured to oscillate an output clock signal in response to the PLL clock signal, and to allow the PLL clock signal to have a frequency that corresponds to a level of the control voltage.

Abstract: A domain crossing circuit of a semiconductor memory apparatus, the domain crossing circuit comprising first and second count signals generated at substantially a same clock period, and representing predetermined clock differences with reference to an internal clock signal with respect to same bit combination data, and a data processing unit configured to provide output data corresponding to input data based on the second count signal in response to the input data synchronized to an external clock signal.

Abstract: A data output circuit includes a pre-driving block configured to receive input data, generate a plurality of pull-up signals and pull-down signals, and change enable times of the pull-up signals and the pull-down signals in response to a plurality of control signals, and a main driving block configured to generate output data in response to the pull-up signals and the pull-down signals.